Topic
Clock domain crossing
About: Clock domain crossing is a research topic. Over the lifetime, 16371 publications have been published within this topic receiving 212390 citations.
Papers published on a yearly basis
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Papers
TL;DR: It is shown that clock frequencies in excess of 200 MHz are feasible in a 3- mu m CMOS process, and a precharge technique with a true single-phase clock, which increases the clock frequency and reduces the skew problems, is used.
Abstract: It is shown that clock frequencies in excess of 200 MHz are feasible in a 3- mu m CMOS process. This performance can be obtained by means of clocking strategy, device sizing, and logic style selection. A precharge technique with a true single-phase clock, which increases the clock frequency and reduces the skew problems, is used. Device sizing with the help of an optimizing program improves circuit speed by a factor of 1.5-1.8. The logic depth is minimized to one instead of two or more, and pipeline structures are used wherever possible. Experimental results for several circuits which work at clock frequencies of 200-230 MHz are presented. SPICE simulation shows that some circuits could work up to 400-500 MHz. >
891 citations
IBM1
TL;DR: A probabilistic method is proposed for reading remote clocks in distributed systems subject to unbounded random communication delays and can achieve clock synchronization precisions superior to those attainable by previously published clock synchronization algorithms.
Abstract: A probabilistic method is proposed for reading remote clocks in distributed systems subject to unbounded random communication delays. The method can achieve clock synchronization precisions superior to those attainable by previously published clock synchronization algorithms. Its use is illustrated by presenting a time service which maintains externally (and hence, internally) synchronized clocks in the presence of process, communication and clock failures.
660 citations
Book•
1 Jan 1996
TL;DR: In this article, a collection of 65 of the most important papers on phase-locked loops and clock recovery circuits is presented, with an extensive 40 page tutorial introduction and a comprehensive coverage of the field all in one self-contained volume.
Abstract: Featuring an extensive 40 page tutorial introduction, this carefully compiled anthology of 65 of the most important papers on phaselocked loops and clock recovery circuits brings you comprehensive coverage of the field-all in one self-contained volume. You'll gain an understanding of the analysis, design, simulation, and implementation of phase-locked loops and clock recovery circuits in CMOS and bipolar technologies along with valuable insights into the issues and trade-offs associated with phase locked systems for high speed, low power, and low noise.
527 citations
TL;DR: Using a model to detect clocking hazards, two linear programs are investigated: minimizing the clock period, while avoiding clock hazards, and for a given period, maximizing the minimum safety margin against clock hazard.
Abstract: Improving the performance of a synchronous digital system by adjusting the path delays of the clock signal from the central clock source to individual flip-flops is investigated. Using a model to detect clocking hazards, two linear programs are investigated: (1) minimizing the clock period, while avoiding clock hazards, and (2) for a given period, maximizing the minimum safety margin against clock hazard. These programs are solved for a simple example, and circuit simulation is used to contrast the operation of a resulting circuit with the conventionally clocked version. The method is extended to account for clock skew caused by relative variations in the drive capabilities of N-channel versus P-channel transistors in CMOS. >
509 citations
Patent•
28 Apr 1994
TL;DR: In this article, the clock is responsive to a digital input signal to control how long it will allow a particular number to remain in the counter before the next clock pulse, so that with each pulse, the value of the counter advances by one.
Abstract: A gaming machine uses a time-based method for generating game results having nonuniform probability. The gaming machine employs an addressable memory in cooperation with a counter and a clock. The clock generates a very fast series of pulses, and includes a digital-to-analog converter. The counter holds a number representing one of the possible reel stop positions and counts the clock's pulses, so that with each pulse, the value of the counter advances by one. To vary the odds that a particular reel stop position will be selected, the clock's pulses do not come at even intervals. Rather, the clock is responsive to a digital input signal to control how long it will allow a particular number to remain in the counter before the next clock pulse. The binary numbers which are used to control the clock are stored in memory. The memory accepts as input the current value of the counter. Thus, when the counter is incremented, the memory provides the binary number associated with the new counter value. By selecting appropriate binary numbers for each possible counter value, the relative amounts of time which the counter holds each value (and, therefore, the probability of selection) can be varied.
404 citations
Related Topics (5)
Performance Metrics
| Year | Papers |
|---|---|
| 2025 | 3 |
| 2024 | 1 |
| 2023 | 31 |
| 2022 | 37 |
| 2021 | 5 |
| 2020 | 9 |