Topic
Clipper architecture
About: Clipper architecture is a research topic. Over the lifetime, 4 publications have been published within this topic receiving 12 citations.
Papers
TL;DR: This 32-bit, three-chip module combines RISC and CISC features with mainframe-style cache and three-phase pipeline designs to create a coherent architecture for next-generation supercomputing.
Abstract: This 32-bit, three-chip module combines RISC and CISC features with mainframe-style cache and three-phase pipeline designs.
6 citations
25 Feb 1991
TL;DR: The C400 represents the first complete reimplementation of the CLIPPER architecture since Fairchild introduced the original C100 version in 1985, and incorporates an entirely new pipeline structure that exploits instruction-level parallelism far more than its predecessors, and provides far greater computational performance than earlierCLIPPERs.
Abstract: The C400 represents the first complete reimplementation of the CLIPPER architecture since Fairchild introduced the original C100 version in 1985. The design incorporates an entirely new pipeline structure that exploits instruction-level parallelism far more than its predecessors, and provides far greater computational performance than earlier CLIPPERs, in both absolute and frequency-adjusted comparisons. The combination of superscalar dispatch and deep floating-point pipelines provides architectural headroom that permits performance enhancements over the life of the implementation architecture. The C400's design goals, constraints, and architecture are discussed. >
5 citations
1 Jan 1991
TL;DR: The C400 represents the first complete reimplementation of CLIPPER architecture since Fairchild introduced the original CZOO version in 2985, and incorporates an entirely new pipeline structure that exploits instruction-level parallelism far more than its predecessors, and provides far greater computational performance than earlier CLIPPERS.
Abstract: The C400 represents the first complete reimplementation of CLIPPER architecture since Fairchild introduced the original CZOO version in 2985. The design incorporates an entirely new pipeline structure that exploits instruction-level parallelism far more than its predecessors, and provides far greater computational performance than earlier CLIPPERS, in both absolute and frequency-adjusted comparisons. The combination of s upe rscala r dispatch and deep floating-point pipelines provides “architectural headroom” that permits performance enhancements over the life of the implementation architecture. This paper discusses the C400’s design goals, constraints, and architecture.
Related Topics (5)
Performance Metrics
| Year | Papers |
|---|---|
| 2002 | 1 |
| 1991 | 2 |
| 1987 | 1 |