Showing papers on "Chip published in 2017"
TL;DR: It is demonstrated that X-ray ptychography—a high-resolution coherent diffractive imaging technique—can create three-dimensional images of integrated circuits of known and unknown designs with a lateral resolution in all directions down to 14.6 nanometres.
Abstract: A recently developed computational imaging technique, X-ray ptychographic tomography, is used to study integrated circuits, and a 3D image of a processor chip with a resolution of 14.6 nm is obtained. As computer chips have become increasingly crammed with nanometre-scale devices and circuitry, new microscopy techniques that can resolve the smallest features are required to enable chip design and inspection. X-ray imaging is uniquely suited for non-destructive, high-resolution imaging and Mirko Holler et al. make use of a recently developed computational imaging technique, X-ray ptychography, to generate high-resolution three-dimensional images of integrated circuits. They test X-ray ptychography on a circuit with known features, and then apply it to an Intel processor chip manufactured in the 22-nanometre technology, obtaining detailed three-dimensional maps of the devices with a resolution down to 14.6 nanometres. This technique could be used to assist quality control during chip production. Modern nanoelectronics1,2 has advanced to a point at which it is impossible to image entire devices and their interconnections non-destructively because of their small feature sizes and the complex three-dimensional structures resulting from their integration on a chip. This metrology gap implies a lack of direct feedback between design and manufacturing processes, and hampers quality control during production, shipment and use. Here we demonstrate that X-ray ptychography3,4—a high-resolution coherent diffractive imaging technique—can create three-dimensional images of integrated circuits of known and unknown designs with a lateral resolution in all directions down to 14.6 nanometres. We obtained detailed device geometries and corresponding elemental maps, and show how the devices are integrated with each other to form the chip. Our experiments represent a major advance in chip inspection and reverse engineering over the traditional destructive electron microscopy and ion milling techniques5,6,7. Foreseeable developments in X-ray sources8, optics9 and detectors10, as well as adoption of an instrument geometry11 optimized for planar rather than cylindrical samples, could lead to a thousand-fold increase in efficiency, with concomitant reductions in scan times and voxel sizes.
436 citations
CERN1
11 Feb 2017-Nuclear Instruments & Methods in Physics Research Section A-accelerators Spectrometers Detectors and Associated Equipment
TL;DR: The ALPIDE chip as mentioned in this paper is a CMOS Monolithic active pixel sensor for the upgrade of the ITS of the ALICE experiment at the CERN Large Hadron Collider (LHC), which is implemented with a 180-nm CMOS imaging process and fabricated on substrates with a high resistivity epitaxial layer.
Abstract: The ALPIDE chip is a CMOS Monolithic Active Pixel Sensor being developed for the Upgrade of the ITS of the ALICE experiment at the CERN Large Hadron Collider. The ALPIDE chip is implemented with a 180 nm CMOS Imaging Process and fabricated on substrates with a high-resistivity epitaxial layer. It measures 15 mm×30 mm and contains a matrix of 512×1024 pixels with in-pixel amplification, shaping, discrimination and multi-event buffering. The readout of the sensitive matrix is hit driven. There is no signaling activity over the matrix if there are no hits to read out and power consumption is proportional to the occupancy. The sensor meets the experimental requirements of detection efficiency above 99%, fake-hit probability below 10 −5 and a spatial resolution of 5 μm. The capability to read out Pb–Pb interactions at 100 kHz is provided. The power density of the ALPIDE chip is projected to be less than 35 mW/cm 2 for the application in the Inner Barrel Layers and below 20 mW/cm 2 for the Outer Barrel Layers, where the occupancy is lower. This contribution describes the architecture and the main features of the final ALPIDE chip, planned for submission at the beginning of 2016. Early results from the experimental qualification of full scale prototype predecessors are also reported.
205 citations
22 Feb 2017
TL;DR: ForeGraph, a large-scale graph processing framework based on the multi-FPGA architecture, is proposed, which outperforms state-of-the-art FPGA-based large- scale graph processing systems by 4.54x when executing PageRank on the Twitter graph.
Abstract: The performance of large-scale graph processing suffers from challenges including poor locality, lack of scalability, random access pattern, and heavy data conflicts. Some characteristics of FPGA make it a promising solution to accelerate various applications. For example, on-chip block RAMs can provide high throughput for random data access. However, large-scale processing on a single FPGA chip is constrained by limited on-chip memory resources and off-chip bandwidth. Using a multi-FPGA architecture may alleviate these problems to some extent, while the data partitioning and communication schemes should be considered to ensure the locality and reduce data conflicts. In this paper, we propose ForeGraph, a large-scale graph processing framework based on the multi-FPGA architecture. In ForeGraph, each FPGA board only stores a partition of the entire graph in off-chip memory. Communication over partitions is reduced. Vertices and edges are sequentially loaded onto the FPGA chip and processed. Under our scheduling scheme, each FPGA chip performs graph processing in parallel without conflicts. We also analyze the impact of system parameters on the performance of ForeGraph. Our experimental results on Xilinx Virtex UltraScale XCVU190 chip show ForeGraph outperforms state-of-the-art FPGA-based large-scale graph processing systems by 4.54x when executing PageRank on the Twitter graph (1.4 billion edges). The average throughput is over 900 MTEPS in our design and 2.03x larger than previous work.
174 citations
20 May 2017
TL;DR: In this article, a wide range continuously tunable optical delay line chip consisting of a ring resonator array and a Mach-Zehnder interferometer (MZI) switch array on the 60-nm-thick silicon waveguide platform is presented.
Abstract: As light cannot be stopped or directly stored in any media, optical delay lines are usually used to temporally trap the optical signals. We report a wide-range continuously tunable optical delay line chip consisting of a ring resonator array and a Mach–Zehnder interferometer (MZI) switch array on the 60-nm-thick silicon waveguide platform. The ring delay line provides continuous delay tuning of more than 10 ps with a push–pull differential tuning method. The MZI switchable delay line provides digitally programmable delay tuning with a resolution of 10 ps upon reconfiguration of the MZI switches to establish different optical routing paths. Dual-stage MZI switches are used to ensure low crosstalk with an improved signal-to-noise ratio. The delay line chip can generate a maximum delay of >1 ns with an on-chip insertion loss of 12.4 dB. Optical pulse time-division multiplexing and quasi-arbitrary waveform generation are realized based on the delay line chip. These results represent a significant step towards the realization of highly reconfigurable optical signal processors enabled by optical delay manipulation with broad applications for optical communications and microwave photonics.
169 citations
TL;DR: A CMOS system on a chip (SoC) for neuroelectrical monitoring and responsive neurostimulation is presented and is validated in vivo using epilepsy monitoring (seizure detection) and treatment ( seizure suppression) experiments.
Abstract: A 64-channel 0.13- $\mu \text{m}$ CMOS system on a chip (SoC) for neuroelectrical monitoring and responsive neurostimulation is presented. The $\Delta \Sigma $ -based neural channel records signals with rail-to-rail dc offset at the input without any area-intensive dc-removing passive components, which leads to a compact 0.013-mm2 integration area of recording and stimulation circuits. The channel consumes 630 nW, yields a signal to noise and distortion ratio of 72.2 dB, a 1.13- $\mu $ Vrms integrated input-referred noise over 0.1–500 Hz frequency range, and a noise efficiency factor of 2.86. Analog multipliers are implemented in each channel with minimum additional area cost by reusing the multi-bit current-digital to analog converter that is originally placed for current-mode stimulation. The multipliers are used for compact implementation of bandpass finite impulse response filters, as well as voltage gain scaling. A tri-core low-power DSP conducts phase-synchrony-based neurophysiological event detection and triggers a subset of 64 programmable arbitrary-waveform current-mode stimulators for subsequent neuromodulation. Two ultra-wideband (UWB) wireless transmitters communicate to receivers located at 10 cm to 2 m distance from the implanted SoC with data rates of 10–46 Mb/s, respectively. An inductive link that operates at 1.5 MHz provides power to the SoC and is also used to communicate commands to an on-chip ASK receiver. The chip occupies 6 mm2 while consuming 1.07 and 5.44 mW with delay-based and voltage controlled oscillator-based UWB transmitters, respectively. The SoC is validated in vivo using epilepsy monitoring (seizure detection) and treatment (seizure suppression) experiments.
158 citations
TL;DR: The time-domain neural network (TDNN), which employs time- domain analog and digital mixed-signal processing (TDAMS) that uses delay time as the analog signal, is proposed, which exploits energy-efficient analog computing, but also enables fully spatially unrolled architecture by the hardware-efficient feature of TDAMS.
Abstract: Demand for highly energy-efficient coprocessor for the inference computation of deep neural networks is increasing. We propose the time-domain neural network (TDNN), which employs time-domain analog and digital mixed-signal processing (TDAMS) that uses delay time as the analog signal. TDNN not only exploits energy-efficient analog computing, but also enables fully spatially unrolled architecture by the hardware-efficient feature of TDAMS. The proposed fully spatially unrolled architecture reduces energy-hungry data moving for weight and activations, thus contributing to significant improvement of energy efficiency. We also propose useful training techniques that mitigate the non-ideal effect of analog circuits, which enables to simplify the circuits and leads to maximizing the energy efficiency. The proof-of-concept chip shows unprecedentedly high energy efficiency of 48.2 TSop/s/W.
141 citations
TL;DR: Methods, circuit techniques and system topology proposed in this work can be used in a wide range of relevant neurophysiology research, especially closed-loop BMI experiments.
Abstract: This paper presents a bidirectional brain machine interface (BMI) microsystem designed for closed-loop neuroscience research, especially experiments in freely behaving animals. The system-on-chip (SoC) consists of 16-channel neural recording front-ends, neural feature extraction units, 16-channel programmable neural stimulator back-ends, in-channel programmable closed-loop controllers, global analog-digital converters (ADC), and peripheral circuits. The proposed neural feature extraction units includes 1) an ultra low-power neural energy extraction unit enabling a 64-step natural logarithmic domain frequency tuning, and 2) a current-mode action potential (AP) detection unit with time-amplitude window discriminator. A programmable proportional-integral-derivative (PID) controller has been integrated in each channel enabling a various of closed-loop operations. The implemented ADCs include a 10-bit voltage-mode successive approximation register (SAR) ADC for the digitization of the neural feature outputs and/or local field potential (LFP) outputs, and an 8-bit current-mode SAR ADC for the digitization of the action potential outputs. The multi-mode stimulator can be programmed to perform monopolar or bipolar, symmetrical or asymmetrical charge balanced stimulation with a maximum current of 4 mA in an arbitrary channel configuration. The chip has been fabricated in 0.18 $\mu$ m CMOS technology, occupying a silicon area of 3.7 mm $^2$ . The chip dissipates 56 $\mu$ W/ch on average. General purpose low-power microcontroller with Bluetooth module are integrated in the system to provide wireless link and SoC configuration. Methods, circuit techniques and system topology proposed in this work can be used in a wide range of relevant neurophysiology research, especially closed-loop BMI experiments.
115 citations
TL;DR: In this article, a cost-aware comparison of isolated bidirectional Si and SiC dual-active-bridge (DAB) concepts for a 5-kW 100-700-V input voltage range dc microgrid application is presented.
Abstract: This work presents a comprehensive cost-aware comparison of isolated bidirectional Si and SiC dual-active-bridge (DAB) concepts for a 5-kW 100–700-V input voltage range dc microgrid application. A conventional three-level DAB (3LDAB) is compared to an advanced five-level DAB (5LDAB) topology, where the latter enables reduced rms currents within the given voltage range. Both concepts employ a loss-optimized modulation scheme enabling zero-voltage switching. A multiobjective optimization routine is proposed to systematically assess the concepts with respect to the efficiency, power density, and the costs. A novel waveform model and advanced component models are considered, which are verified using a hardware prototype. The calculated Pareto fronts show that SiC MOSFETs enable significantly higher efficiencies and power densities than Si IGBTs, while similar costs can be achieved. The performance comparison between the SiC MOSFET-based 3LDAB and 5LDAB reveals a fundamental superiority of the 3LDAB, which is mainly due to the higher chip area utilization and the lower component count of this concept. Finally, the calculations and the hardware prototype prove that despite the galvanic isolation and wide voltage range, efficiencies above 98 % in a wide operating range are possible, which was previously not seen in the literature.
111 citations
TL;DR: In this article, a 2-channel frequency division multiplexing (FDM) and polarization division multiple access (PDM) scheme was used for short-distance wireless communications in the terahertz (THz) range.
Abstract: High-capacity short-distance wireless communications in the terahertz (THz) range are anticipated and therefore have been intensively studied. Higher data rates are made possible by the introduction of frequency division multiplexing (FDM) and polarization division multiplexing (PDM) schemes in the THz range. In this paper, wireless data transmissions using 2-channel FDM in the 500 and 800 GHz ranges and PDM in the 500 GHz range are demonstrated using resonant-tunneling-diode oscillators with different frequencies and polarizations integrated into one chip. Transmissions at a data rate of 28 Gbit/s were achieved in each channel with an error rate below the forward error correction limit in both multiplexing systems. The ratios of the leakage of the transmitted signal in one channel into the other channel were about −40 and −30 dB in FDM and PDM modes, respectively.
102 citations
TL;DR: This work demonstrates the retrieval of three sparse input signals by collecting data from restricted sets of MZIs and applying common CS reconstruction techniques to this data, and shows that this retrieval maintains the full resolution and bandwidth of the original device, despite a sampling factor as low as one-fourth of a conventional (non-compressive) design.
Abstract: We demonstrate compressive-sensing (CS) spectroscopy in a planar-waveguide Fourier-transform spectrometer (FTS) device. The spectrometer is implemented as an array of Mach–Zehnder interferometers (MZIs) integrated on a photonic chip. The signal from a set of MZIs is composed of an undersampled discrete Fourier interferogram, which we invert using l1-norm minimization to retrieve a sparse input spectrum. To implement this technique, we use a subwavelength-engineered spatial heterodyne FTS on a chip composed of 32 independent MZIs. We demonstrate the retrieval of three sparse input signals by collecting data from restricted sets (8 and 14) of MZIs and applying common CS reconstruction techniques to this data. We show that this retrieval maintains the full resolution and bandwidth of the original device, despite a sampling factor as low as one-fourth of a conventional (non-compressive) design.
92 citations
TL;DR: This work investigates the online learning approach by training an optoelectronic reservoir computer using a simple gradient descent algorithm, programmed on a field-programmable gate array chip, and shows that its system is particularly well suited for realistic channel equalization.
Abstract: Reservoir computing is a bioinspired computing paradigm for processing time-dependent signals. The performance of its analog implementation is comparable to other state-of-the-art algorithms for tasks such as speech recognition or chaotic time series prediction, but these are often constrained by the offline training methods commonly employed. Here, we investigated the online learning approach by training an optoelectronic reservoir computer using a simple gradient descent algorithm, programmed on a field-programmable gate array chip. Our system was applied to wireless communications, a quickly growing domain with an increasing demand for fast analog devices to equalize the nonlinear distorted channels. We report error rates up to two orders of magnitude lower than previous implementations on this task. We show that our system is particularly well suited for realistic channel equalization by testing it on a drifting and a switching channel and obtaining good performances.
TL;DR: In this article, a dual-comb spectrometer based on two passively mode-locked waveguide lasers integrated in a single Er-doped ZBLAN chip is presented.
Abstract: We present a dual-comb spectrometer based on two passively mode-locked waveguide lasers integrated in a single Er-doped ZBLAN chip. This original design yields two free-running frequency combs having a high level of mutual stability. We developed in parallel a self-correction algorithm that compensates residual relative fluctuations and yields mode-resolved spectra without the help of any reference laser or control system. Fluctuations are extracted directly from the interferograms using the concept of ambiguity function, which leads to a significant simplification of the instrument that will greatly ease its widespread adoption and commercial deployment. Comparison with a correction algorithm relying on a single-frequency laser indicates discrepancies of only 50 attoseconds on optical timings. The capacities of this instrument are finally demonstrated with the acquisition of a high-resolution molecular spectrum covering 20 nm. This new chip-based multi-laser platform is ideal for the development of high-repetition-rate, compact and fieldable comb spectrometers in the near- and mid-infrared.
TL;DR: This paper presents a packaged 76- to 81-GHz transceiver chip implemented in SiGe BiCMOS for both long-range and short-range automotive radars and integrated BIST circuits enable the measurement of signal power, RX gain, channel-to-channel phase, and internal temperature.
Abstract: This paper presents a packaged 76- to 81-GHz transceiver chip implemented in SiGe BiCMOS for both long-range and short-range automotive radars. The chip contains a two-channel transmitter (TX), a six-channel receiver (RX), a local-oscillator (LO) chain, and built-in self-test (BIST) circuitry. Each transmit channel includes multiple variable-gain amplifiers and a two-stage power amplifier. Measured on-die output power per channel is +18 dBm at 25 °C, decreasing to +16 dBm at 125 °C. Each receive channel includes a current-mode mixer, followed by intermediate-frequency buffers. At 25 °C, measured on-die noise figure is 10–11 dB, conversion gain is 14–15 dB, and input 1-dB compression point exceeds +1 dBm. An integrated LO chain drives the transmit and receive chains and includes an 18.5- to 20.6-GHz voltage-controlled oscillator connected to cascaded frequency doublers and a divide-by-four prescaler. At 25 °C, measured phase noise is −100 dBc/Hz at 1-MHz offset from a 77-GHz carrier. Integrated BIST circuits enable the measurement of signal power, RX gain, channel-to-channel phase, and internal temperature. The chip is flip-chip packaged into a ball-grid array and extracted interconnect loss for the package is 1.5 to 2 dB. Total power consumption for the chip is 1.8 W from 3.3 V for a single-TX, six-RX mode.
TL;DR: A 6.4 MS/s 13 b ADC with a low-power background calibration for DAC mismatch and comparator offset errors is presented and achieves 20 dB spur reduction with little area and power overhead.
Abstract: A 6.4 MS/s 13 b ADC with a low-power background calibration for DAC mismatch and comparator offset errors is presented. Redundancy deals with DAC settling and facilitates calibration. A two-mode comparator and 0.3 fF capacitors reduce power and area. The background calibration can directly detect the sign of the dynamic comparator offset error and the DAC mismatch errors and correct both of them simultaneously in a stepwise feedback loop. The calibration achieves 20 dB spur reduction with little area and power overhead. The chip is implemented in 40 nm CMOS and consumes 46 $\mu \text{W}$ from a 1 V supply, and achieves 64.1 dB SNDR and a FoM of 5.5 fJ/conversion-step at Nyquist.
TL;DR: A self-correction algorithm is developed in parallel that compensates residual relative fluctuations and yields mode-resolved spectra without the help of any reference laser or control system.
Abstract: We present a dual-comb spectrometer based on two passively mode-locked waveguide lasers integrated in a single Er-doped ZBLAN chip. This original design yields two free-running frequency combs having a high level of mutual stability. We developed in parallel a self-correction algorithm that compensates residual relative fluctuations and yields mode-resolved spectra without the help of any reference laser or control system. Fluctuations are extracted directly from the interferograms using the concept of ambiguity function, which leads to a significant simplification of the instrument that will greatly ease its widespread adoption. Comparison with a correction algorithm relying on a single-frequency laser indicates discrepancies of only 50 attoseconds on optical timings. The capacities of this instrument are finally demonstrated with the acquisition of a high-resolution molecular spectrum covering 20 nm. This new chip-based multi-laser platform is ideal for the development of high-repetition-rate, compact and fieldable comb spectrometers in the near- and mid-infrared.
TL;DR: An exquisite scalable self-priming fractal branching microchannel net digital PCR chip with an even distribution and 100% compartmentalization of the sample without any sample loss, which is not available in existing chip-based digital PCR methods is developed.
Abstract: As an absolute quantification method at the single-molecule level, digital PCR has been widely used in many bioresearch fields, such as next generation sequencing, single cell analysis, gene editing detection and so on. However, existing digital PCR methods still have some disadvantages, including high cost, sample loss, and complicated operation. In this work, we develop an exquisite scalable self-priming fractal branching microchannel net digital PCR chip. This chip with a special design inspired by natural fractal-tree systems has an even distribution and 100% compartmentalization of the sample without any sample loss, which is not available in existing chip-based digital PCR methods. A special 10 nm nano-waterproof layer was created to prevent the solution from evaporating. A vacuum pre-packaging method called self-priming reagent introduction is used to passively drive the reagent flow into the microchannel nets, so that this chip can realize sequential reagent loading and isolation within a couple of minutes, which is very suitable for point-of-care detection. When the number of positive microwells stays in the range of 100 to 4000, the relative uncertainty is below 5%, which means that one panel can detect an average of 101 to 15 374 molecules by the Poisson distribution. This chip is proved to have an excellent ability for single molecule detection and quantification of low expression of hHF-MSC stem cell markers. Due to its potential for high throughput, high density, low cost, lack of sample and reagent loss, self-priming even compartmentalization and simple operation, we envision that this device will significantly expand and extend the application range of digital PCR involving rare samples, liquid biopsy detection and point-of-care detection with higher sensitivity and accuracy.
TL;DR: In this article, the use of a low-loss, high-index-contrast stoichiometric silicon nitride waveguide is presented as a practical material platform for realizing high-performance optical signal processors and points toward photonic RF filters with digital signal processing level flexibility, hundreds-GHz bandwidth, MHz-band frequency selectivity, and full system integration on a chip scale.
Abstract: Integrated optical signal processors have been identified as a powerful engine for optical processing of microwave signals. They enable wideband and stable signal processing operations on miniaturized chips with ultimate control precision. As a promising application, such processors enables photonic implementations of reconfigurable radio frequency (RF) filters with wide design flexibility, large bandwidth, and high-frequency selectivity. This is a key technology for photonic-assisted RF front ends that opens a path to overcoming the bandwidth limitation of current digital electronics. Here, the recent progress of integrated optical signal processors for implementing such RF filters is reviewed. We highlight the use of a low-loss, high-index-contrast stoichiometric silicon nitride waveguide which promises to serve as a practical material platform for realizing high-performance optical signal processors and points toward photonic RF filters with digital signal processing (DSP)-level flexibility, hundreds-GHz bandwidth, MHz-band frequency selectivity, and full system integration on a chip scale.
TL;DR: In this paper, a mobile sensor for on-site analysis of soil sample extracts is presented, which mainly consists of a microfluidic chip in which the sample ions are separated in an electric field (capillary electrophoresis) and the individual ion concentrations are detected by a conductivity measurement.
Abstract: In this paper, a mobile sensor for on-site analysis of soil sample extracts is presented. As a versatile tool for scanning ion concentrations in liquid samples, it especially allows the analysis of NO3, NH4, K and PO4. The sensor mainly consists of a microfluidic chip in which the sample ions are separated in an electric field (capillary electrophoresis) and the individual ion concentrations are detected by a conductivity measurement. For the adaption of the device to field conditions, two major concerns were addressed. Firstly, nano-porous material was used as a barrier between the sample container and the analysis channel of the microfluidic chip. This prevents pressure driven leakage of the sample into the chip due to non-horizontal orientation of the device. Secondly, a new method for the injection of the sample into the chip was used. It reduces the number of fluidic connections between chip and operation device to three instead of the commonly used four connections. The sensor performance was tested on multi-ion solutions with calibration series for NO3, NH4, K and PO4. For the first on-site test, a quick soil nutrient extraction procedure with water was used. The sensor data was compared to standard laboratory results. The potential of the sensor for soil nutrient analysis is discussed together with required improvements of the sensor performance and of the nutrient extraction procedure.
TL;DR: In this article, a switched-capacitor matrix multiplier is presented for approximate computing and machine learning applications, which performs discrete-time charge-domain signal processing using passive switches and 300 aF unit capacitors.
Abstract: A switched-capacitor matrix multiplier is presented for approximate computing and machine learning applications. The multiply-and-accumulate operations perform discrete-time charge-domain signal processing using passive switches and 300 aF unit capacitors. The computation is digitized with a 6 b asynchronous successive approximation register analog-to-digital converter. The analyses of incomplete charge accumulation and thermal noise are discussed. The design was fabricated in 40 nm CMOS, and experimental measurements of multiplication are illustrated using matched filtering and image convolutions to analyze noise and offset. Two applications are highlighted: 1) energy-efficient feature extraction layer performing both compression and classification in a neural network for an analog front end and 2) analog acceleration for solving optimization problems that are traditionally performed in the digital domain. The chip obtains measured efficiencies of 8.7 TOPS/W at 1 GHz for the first application and 7.7 TOPS/W at 2.5 GHz for the second application.
TL;DR: In this paper, the authors developed a coupled behavior and damage model for better representation and understanding of the chip formation process in the Ti-6Al-4V machining process, which is described by three steps: growth, germination and extraction.
4 Jun 2017
TL;DR: In this article, a 0 mW two-channel 28 GHz bi-directional phased array chip was presented using flip-chip interconnects in 45nm CMOS SOI.
Abstract: This paper presents a 0 mW two-channel 28 GHz bi-directional phased-array chip packaged using flip-chip interconnects in 45nm CMOS SOI. The design alternates switched-LC phase shifters with switched attenuators to result in 5-bit phase control with an rms gain and phase error 1dB of 5 dBm. In the TX mode, the measured output P 1dB is −2 dBm. This work presents an efficient solution for the construction of high-linearity and high-power phased-array base-stations by combining GaAs front-ends with a passive silicon core chip.
Lund University1, University of São Paulo2, Oak Ridge National Laboratory3, University of Paris-Sud4, State University of Campinas5, Brookhaven National Laboratory6, University of Oslo7, Instituto Tecnológico de Aeronáutica8, Joint Institute for Nuclear Research9, University of Bergen10, Universidade Federal de Santa Catarina11
TL;DR: The test results of the second prototype of SAMPA, the ASIC designed for the upgrade of read-out front end electronics of the ALICE Time Projection Chamber (TPC) and Muon Chamber (MCH), are presented.
Abstract: This paper presents the test results of the second prototype of SAMPA, the ASIC designed for the upgrade of read-out front end electronics of the ALICE Time Projection Chamber (TPC) and Muon Chamber (MCH). SAMPA is made in a 130 nm CMOS technology with 1.25 V nominal voltage supply and provides 32 channels, with selectable input polarity, and three possible combinations of shaping time and sensitivity. Each channel consists of a Charge Sensitive Amplifier, a semi-Gaussian shaper and a 10-bit ADC; a Digital Signal Processor provides digital filtering and compression capability. In the second prototype run both full chip and single test blocks were fabricated, allowing block characterization and full system behaviour studies. Experimental results are here presented showing agreement with requirements for both the blocks and the full chip.
TL;DR: A droplet-based microfluidic device with seamless hyphenation to electrospray mass spectrometry was developed to rapidly investigate organic reactions in segmented flow providing a versatile tool for drug development.
Abstract: A droplet-based microfluidic device with seamless hyphenation to electrospray mass spectrometry was developed to rapidly investigate organic reactions in segmented flow providing a versatile tool for drug development. A chip-MS interface with an integrated counterelectrode allowed for a flexible positioning of the chip-emitter in front of the MS orifice as well as an independent adjustment of the electrospray potentials. This was necessary to avoid contamination of the mass spectrometer as well as sample overloading due to the high analyte concentrations. The device was exemplarily applied to study the scope of an amino-catalyzed domino reaction with low picomole amount of catalyst in individual nanoliter sized droplets.
TL;DR: In this paper, the authors investigated the wireless network-on-chip (WiNoC), which is enabled by graphene-based nanoantennas (GNAs) in the Terahertz frequency band, and proposed an optimal power allocation to achieve the channel capacity.
Abstract: One of the main challenges towards the growing computation-intensive applications with scalable bandwidth requirement is the deployment of a dense number of on-chip cores within a chip package To this end, this paper investigates the Wireless Network-on-Chip (WiNoC), which is enabled by graphene-based nanoantennas (GNAs) in Terahertz frequency band We first develop a channel model between the GNAs taking into account the practical issues of the propagation medium, such as transmission frequency, operating temperature, ambient pressure, and distance between the GNAs In the Terahertz band, not only dielectric propagation loss but also molecular absorption attenuation (MAA) caused by various molecules and their isotopologues within the chip package constitutes the signal transmission loss We further propose an optimal power allocation to achieve the channel capacity The proposed channel model shows that the MAA significantly degrades the performance at certain frequency ranges compared to the conventional channel model, even when the GNAs are very closely located More specifically, at transmission frequency of 1 THz, the channel capacity of the proposed model is shown to be much lower than that of the conventional model over the whole range of temperature and ambient pressure of up to 268% and 25%, respectively
1 Dec 2017
TL;DR: In this article, a stacked pixel/DRAM/logic based image sensor (CIS) was developed, where three Si substrates are bonded together and each substrate is electrically connected by two-stacked through-silica vias (TSVs) through the CIS or dynamic random access memory (DRAM).
Abstract: We developed a CMOS image sensor (CIS) chip, which is stacked pixel/DRAM/logic. In this CIS chip, three Si substrates are bonded together, and each substrate is electrically connected by two-stacked through-silica vias (TSVs) through the CIS or dynamic random access memory (DRAM). We obtained low resistance, low leakage current, and high reliability characteristics of these TSVs. Connecting metal with TSVs through DRAM can be used as low resistance wiring for a power supply. The Si substrate of the DRAM can be thinned to 3 pm, and its memory retention and operation characteristics are sufficient for specifications after thinning. With this stacked CIS chip, it is possible to achieve less rolling shutter distortion and produce super slow motion video.
20 Jul 2017
TL;DR: In this article, the authors proposed a hybrid silicon photonic chip based on III-V/silicon-on-insulator photonic integration for an fiber Bragg grating (FBG) interrogator.
Abstract: Silicon photonic integration is a means to produce an integrated on-chip fiber Bragg grating (FBG) interrogator. The possibility of integrating the light source, couplers, grating couplers, de-multiplexers, photodetectors (PDs), and other optical elements of the FBG interrogator into one chip may result in game-changing performance advances, considerable energy savings, and significant cost reductions. To the best of our knowledge, this paper is the first to present a hybrid silicon photonic chip based on III–V/silicon-on-insulator photonic integration for an FBG interrogator. The hybrid silicon photonic chip consists of a multiwavelength vertical-cavity surface-emitting laser array and input grating couplers, a multimode interference coupler, an arrayed waveguide grating, output grating couplers, and a PD array. The chip can serve as an FBG interrogator on a chip and offer unprecedented opportunities. With a footprint of 5 mm×3 mm, the proposed hybrid silicon photonic chip achieves an interrogation wavelength resolution of approximately 1 pm and a wavelength accuracy of about ±10 pm. With the measured 1 pm wavelength resolution, the temperature measurement resolution of the proposed chip is approximately 0.1°C. The proposed hybrid silicon photonic chip possesses advantages in terms of cost, manufacturability, miniaturization, and performance. The chip supports applications that require extreme miniaturization down to the level of smart grains.
TL;DR: An experimental demonstration of a photonic integrated silicon chip quantum key distribution protocols based on space division multiplexing (SDM) through multicore fiber technology, which achieves parallel and independent quantum keys, which are useful in crypto-systems and future quantum network.
Abstract: Quantum cryptography is set to become a key technology for future secure communications. However, to get maximum benefit in communication networks, transmission links will need to be shared among several quantum keys for several independent users. Such links will enable switching in quantum network nodes of the quantum keys to their respective destinations. In this paper we present an experimental demonstration of a photonic integrated silicon chip quantum key distribution protocols based on space division multiplexing (SDM), through multicore fiber technology. Parallel and independent quantum keys are obtained, which are useful in crypto-systems and future quantum network.
TL;DR: In this article, the authors simulated statically placed single-fault lattices and lattices with randomly placed faults at functional qubit yields of 80, 90, and 95, showing practical performance of a defective surface code by employing actual circuit constructions and realistic errors on every gate.
Abstract: The yield of physical qubits fabricated in the laboratory is much lower than that of classical transistors in production semiconductor fabrication. Actual implementations of quantum computers will be susceptible to loss in the form of physically faulty qubits. Though these physical faults must negatively affect the computation, we can deal with them by adapting error-correction schemes. In this paper we have simulated statically placed single-fault lattices and lattices with randomly placed faults at functional qubit yields of 80%, 90%, and 95%, showing practical performance of a defective surface code by employing actual circuit constructions and realistic errors on every gate, including identity gates. We extend Stace et al's superplaquettes solution against dynamic losses for the surface code to handle static losses such as physically faulty qubits [1]. The single-fault analysis shows that a static loss at the periphery of the lattice has less negative effect than a static loss at the center. The randomly faulty analysis shows that 95% yield is good enough to build a large-scale quantum computer. The local gate error rate threshold is , and a code distance of seven suppresses the residual error rate below the original error rate at . 90% yield is also good enough when we discard badly fabricated quantum computation chips, while 80% yield does not show enough error suppression even when discarding 90% of the chips. We evaluated several metrics for predicting chip performance, and found that the average of the product of the number of data qubits and the cycle time of a stabilizer measurement of stabilizers gave the strongest correlation with logical error rates. Our analysis will help with selecting usable quantum computation chips from among the pool of all fabricated chips.
TL;DR: The device described here contains four easily integrated electrodes that are placed and fixed outside of the culture area, making visual inspection possible and the resistance of six measurement paths can be quantified, from which the TEER can be directly isolated, independent of the Resistance of culture medium-filled microchannels.
Abstract: Organs-on-chips, in vitro models involving the culture of (human) tissues inside microfluidic devices, are rapidly emerging and promise to provide useful research tools for studying human health and disease. To characterize the barrier function of cell layers cultured inside organ-on-chip devices, often transendothelial or transepithelial electrical resistance (TEER) is measured. To this end, electrodes are usually integrated into the chip by micromachining methods to provide more stable measurements than is achieved with manual insertion of electrodes into the inlets of the chip. However, these electrodes frequently hamper visual inspection of the studied cell layer or require expensive cleanroom processes for fabrication. To overcome these limitations, the device described here contains four easily integrated electrodes that are placed and fixed outside of the culture area, making visual inspection possible. Using these four electrodes the resistance of six measurement paths can be quantified, from which the TEER can be directly isolated, independent of the resistance of culture medium-filled microchannels. The blood-brain barrier was replicated in this device and its TEER was monitored to show the device applicability. This chip, the integrated electrodes and the TEER determination method are generally applicable in organs-on-chips, both to mimic other organs or to be incorporated into existing organ-on-chip systems.
TL;DR: In this paper, a fewmode (FM) vertical cavity surface emitting laser (VCSEL) chip with heavily zinc-diffused contact layer and oxide-confined cross-section is demonstrated for carrying pre-leveled 16-quadrature amplitude modulation orthogonal frequency division multiplexing (QAM-OFDM) data in OM4 multi-mode fiber (MMF) over 100m for intra-data-center applications.
Abstract: A few-mode (FM) vertical cavity surface emitting laser (VCSEL) chip with heavily zinc-diffused contact layer and oxide-confined cross-section is demonstrated for carrying pre-leveled 16-quadrature amplitude modulation orthogonal frequency division multiplexing (QAM-OFDM) data in OM4 multi-mode fiber (MMF) over 100 m for intra-data-center applications. The FM VCSEL chip, which has an oxide-confined emission aperture of 5 μm, demonstrates high external quantum efficiency, provides an optical power of 2.2 mW at 38 times threshold condition, and exhibits 3 dB direct-modulation bandwidth beyond 22 GHz at a cost of slight heat accumulation. At a DC bias point of 5 mA (22.6Ith) the FM VCSEL chip, with sufficiently normalized modulation output, supports Baud and data rates of 25 and 100 Gb/s, respectively, with forward error correction (FEC) certifying receiving quality after back-to-back transmission. After passing through 100 m OM4 MMF with a receiving power penalty of 4 dB, the FM VCSEL chip demonstrates FEC-certified transmission of the pre-leveled 16-QAM OFDM data at 92 Gb/s.