Showing papers on "Chip published in 2015"
TL;DR: This demonstration could represent the beginning of an era of chip-scale electronic–photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.
Abstract: An electronic–photonic microprocessor chip manufactured using a conventional microelectronics foundry process is demonstrated; the chip contains 70 million transistors and 850 photonic components and directly uses light to communicate to other chips. The rapid transfer of data between chips in computer systems and data centres has become one of the bottlenecks in modern information processing. One way of increasing speeds is to use optical connections rather than electrical wires and the past decade has seen significant efforts to develop silicon-based nanophotonic approaches to integrate such links within silicon chips, but incompatibility between the manufacturing processes used in electronics and photonics has proved a hindrance. Now Chen Sun et al. describe a 'system on a chip' microprocessor that successfully integrates electronics and photonics yet is produced using standard microelectronic chip fabrication techniques. The resulting microprocessor combines 70 million transistors and 850 photonic components and can communicate optically with the outside world. This result promises a way forward for new fast, low-power computing systems architectures. Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems—from mobile phones to large-scale data centres. These limitations can be overcome1,2,3 by using optical communications based on chip-scale electronic–photonic systems4,5,6,7 enabled by silicon-based nanophotonic devices8. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic–photonic chips9,10,11 are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic–photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a ‘zero-change’ approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics12, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors13,14,15,16. This demonstration could represent the beginning of an era of chip-scale electronic–photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.
1,321 citations
20 Feb 2015
TL;DR: In this paper, a chip-based MWP bandstop filter with ultrahigh suppression, high resolution in the megahertz range, and 0-30 GHz frequency tuning is presented. But the performance is limited by trade-offs between key parameters such as tuning range, resolution, and suppression.
Abstract: Highly selective and reconfigurable microwave filters are of great importance in radio-frequency signal processing. Microwave photonic (MWP) filters are of particular interest, as they offer flexible reconfiguration and an order of magnitude higher frequency tuning range than electronic filters. However, all MWP filters to date have been limited by trade-offs between key parameters such as tuning range, resolution, and suppression. This problem is exacerbated in the case of integrated MWP filters, blocking the path to compact, high-performance filters. Here we show the first chip-based MWP bandstop filter with ultrahigh suppression, high resolution in the megahertz range, and 0–30 GHz frequency tuning. This record performance was achieved using an ultralow Brillouin gain from a compact photonic chip and a novel approach of optical resonance-assisted RF signal cancellation. The results point to new ways of creating energy-efficient and reconfigurable integrated MWP signal processors for wireless communications and defence applications.
386 citations
TL;DR: A 512 × 424 time-of-flight (TOF) depth image sensor designed in a TSMC 0.13 μm LP 1P5M CMOS process, suitable for use in Microsoft Kinect for XBOX ONE, shows wide depth range of operation, small accuracy error, very low depth uncertainty, and very high dynamic range.
Abstract: We introduce a 512 × 424 time-of-flight (TOF) depth image sensor designed in a TSMC 0.13 μm LP 1P5M CMOS process, suitable for use in Microsoft Kinect for XBOX ONE. The 10 μm × 10 μm pixel incorporates a TOF detector that operates using the quantum efficiency modulation (QEM) technique at high modulation frequencies of up to 130 MHz, achieves a modulation contrast of 67% at 50 MHz and a responsivity of 0.14 A/W at 860 nm. The TOF sensor includes a 2 GS/s 10 bit signal path, which is used for the high ADC bandwidth requirements of the system that requires many ADC conversions per frame. The chip also comprises a clock generation circuit featuring a programmable phase and frequency clock generator with 312.5-ps phase step resolution derived from a 1.6 GHz oscillator. An integrated shutter engine and a programmable digital micro-sequencer allows an extremely flexible multi-gain/multi-shutter and multi-frequency/multi-phase operation. All chip data is transferred using two 4-lane MIPI D-PHY interfaces with a total of 8 Gb/s input/output bandwidth. The reported experimental results demonstrate a wide depth range of operation (0.8–4.2 m), small accuracy error ( $ 1%), very low depth uncertainty ( $ 0.5% of actual distance), and very high dynamic range ( $>$ 64 dB).
228 citations
TL;DR: By analyzing and comparing features of these technologies, a research direction of guiding on future 5G multiple access and waveform are given.
Abstract: One key advantage of 4G OFDM system is the relatively simple receiver implementation due to the orthogonal resource allocation. However, from sum-capacity and spectral efficiency points of view, orthogonal systems are never the achieving schemes. With the rapid development of mobile communication systems, a novel concept of non-orthogonal transmission for 5G mobile communications has attracted researches all around the world. In this trend, many new multiple access schemes and waveform modulation technologies were proposed. In this paper, some promising ones of them were discussed which include Non-orthogonal Multiple Access (NOMA), Sparse Code Multiple Access (SCMA), Multi-user Shared Access (MUSA), Pattern Division Multiple Access (PDMA) and some main new waveforms including Filter-bank based Multicarrier (FBMC), Universal Filtered Multi-Carrier (UFMC), Generalized Frequency Division Multiplexing (GFDM). By analyzing and comparing features of these technologies, a research direction of guiding on future 5G multiple access and waveform are given.
206 citations
TL;DR: A new method of building the joint RF and baseband precoder that reduces the computation complexity of the original precoder reconstruction algorithm and enables highly parallel hardware architecture is proposed.
Abstract: A millimeter wave (mm-wave) communication system provides multi-Gb/s data rates in short-distance transmission. Because millimeter waves have short wavelength, transceivers can be composed of large antenna arrays to alleviate severe signal attenuation. Furthermore, the link performance can be improved by adopting precoding technology in multiple data stream transmission. However, the complexity of radio frequency (RF) chains increases when large antenna arrays are used in mm-wave systems. To reduce the hardware cost, the precoding circuit can be jointly designed in both analog and digital domains to reduce the required number of RF chains. This paper proposes a new method of building the joint RF and baseband precoder that reduces the computation complexity of the original precoder reconstruction algorithm and enables highly parallel hardware architecture. Moreover, the proposed precoder reconstruction algorithm was designed and implemented using TSMC 90-nm UTM CMOS technology. The proposed precoder reconstruction processor supports the transmissions of one to four data streams for 8 × 8 mm-wave multiple-input multiple-output systems. The operating frequency of this chip was 167 MHz, and the power consumption was 243.2 mW when the supply voltage was 1 V. The core area of the postlayout result was about 3.94 mm 2
. The proposed processor achieved 4, 4.9, 6.7, and 6.7 M channel matrices per second in four-, three-, two-, and one-stream modes, respectively.
202 citations
Patent•
23 Jun 2015
TL;DR: In this article, a one-dimensional planar beam forming and steering optical phased array chip is used as a simple building block of a two-dimensional beamforming and steering solid-state lidar.
Abstract: A one-dimensional planar beam forming and steering optical phased array chip is a simple building block of a two-dimensional beam forming and steering solid-state lidar, enabling manufacturing of said lidars at high yield and low cost through the use of a plurality of said chips. Innovative photonic integrated circuit chip architectures that follow design for manufacturing rules enable said building blocks.
121 citations
1 Feb 2015
TL;DR: Physical unclonable functions (PUFs) were proposed as a secure method for chip authentication in unsecure environments and are increasingly used for IC authentication to offer protection against identity theft, cloning, and counterfeit components.
Abstract: Security is a key concern in today's mobile devices and a number of hardware implementations of security primitives have been proposed, including true random number generators, differential power attack avoidance, and chip-ID generators [1-4]. Recently, physically unclonable functions (PUFs) were proposed as a secure method for chip authentication in unsecure environments [5-7]. A PUF is a function that maps an input code ("challenge') to an output code (“response”) in a manner that is unique for every chip. PUFs are increasingly used for IC authentication to offer protection against identity theft, cloning, and counterfeit components [2-4].
117 citations
TL;DR: This work demonstrates a silicon-photonic link with optical devices and electronics integrated on the same chip in a 0.18 µm bulk CMOS memory periphery process, and introduces deep-trench isolation, placed underneath to prevent optical mode leakage into the bulk silicon substrate, and implant-amorphization to reduce polysilicon loss.
Abstract: Silicon-photonics is an emerging technology that can overcome the tradeoffs faced by traditional electrical I/O. Due to ballooning development costs for advanced CMOS nodes, however, widespread adoption necessitates seamless photonics integration into mainstream processes, with as few process changes as possible. In this work, we demonstrate a silicon-photonic link with optical devices and electronics integrated on the same chip in a 0.18 µm bulk CMOS memory periphery process. To enable waveguides and optics in process-native polysilicon, we introduce deep-trench isolation, placed underneath to prevent optical mode leakage into the bulk silicon substrate, and implant-amorphization to reduce polysilicon loss. A resonant defect-trap photodetector using polysilicon eliminates need for germanium integration and completes the fully polysilicon-based photonics platform. Transceiver circuits take advantage of photonic device integration, achieving 350 fJ/b transmit and 71 µA pp BER = 10 -12 receiver sensitivity at 5 Gb/s. We show high fabrication uniformity and high-Q resonators, enabling dense wavelength-division multiplexing with 9-wavelength 45 Gb/s transmit/receive data-rates per waveguide/fiber. To combat perturbations to variation- and thermally-sensitive resonant devices, we demonstrate an on-chip thermal tuning feedback loop that locks the resonance to the laser wavelength. A 5 m optical chip-to-chip link achieves 5 Gb/s while consuming 3 pJ/b and 12 pJ/bit of circuit and optical energy, respectively.
93 citations
24 May 2015
TL;DR: The design of a 1mW, 10ns-latency mixed signal system in 0.18μm CMOS which enables filtering out uncorrelated background activity in event-based neuromorphic sensors and targets embedded neuromorphic visual and auditory systems, where low average power consumption and low latency are critical.
Abstract: This paper reports the design of a 1mW, 10ns-latency mixed signal system in 0.18μm CMOS which enables filtering out uncorrelated background activity in event-based neuromorphic sensors. Background activity (BA) in the output of dynamic vision sensors is caused by thermal noise and junction leakage current acting on switches connected to floating nodes in the pixels. The reported chip generates a pass flag for spatiotemporally correlated events for post-processing to reduce communication/computation load and improve information rate. A chip with 128×128 array with 20×20μm2 cells has been designed. Each filter cell combines programmable spatial subsampling with a temporal window based on current integration. Power-gating is used to minimize the power consumption by only activating the threshold detection and communication circuits in the cell receiving an input event. This correlation filter chip targets embedded neuromorphic visual and auditory systems, where low average power consumption and low latency are critical.
92 citations
TL;DR: In this article, the authors explored the general framework and prospects for on-chip and off-chip wireless interconnects implemented for high-performance computing (HPC) systems in the context of micro power wireless design.
Abstract: This paper explores the general framework and prospects for on-chip and off-chip wireless interconnects implemented for high-performance computing (HPC) systems in the context of micro power wireless design. HPC interconnects demand very high (≥ 10 Gb/s) transmission rates using ultraefficient ( $\sim ~1$ pJ/bit) transceivers over extremely short (≤ 100 cm) ranges. In an attempt to design such wireless interconnects, first a model for the wireless communication channel properties is developed. The use of CMOS-based energy-efficient on–off keying (OOK) transceiver architectures operating in the 60–90 GHz bands is considered as a practical solution. In order to address strict performance requirements of wireless HPC interconnects, and taking advantage of the recent developments in device scaling, compact low-power and innovative circuits based on novel double-gate MOSFETs (DG-MOSFETs) are proposed in the implementation of the architecture. The performance of a compact low-noise amplifier (LNA) design using common source (CS) inductive degeneration with 32 nm DG-MOSFETs is investigated by quantitative analysis and simulation. The proposed inductor-less two-stage cascode cascade LNA is optimized for 90 GHz operation and has the advantage of gain switching over its CMOS counterpart without the use of additional switching transistors, which makes it remarkably power efficient and faster. As further examples of efficient and compact DG-MOSFET circuits for OOK transceiver design, a three-stage CS 5 dB tunable power amplifier operating up to 90 GHz, and a novel 90 GHz voltage controlled oscillator are also presented. This is followed by the proposal of an array of four monopole antennas studied using full-wave EM solver.
92 citations
Patent•
14 Jul 2015
TL;DR: In this article, the authors proposed a light coupling integration technique to realize integrated laser and photonic integrated circuits on complimentary metal-oxide semiconductor (CMOS)-compatible silicon (Si) photonic chips, potentially containing integrated electronics.
Abstract: Methods for realizing integrated lasers and photonic integrated circuits on complimentary metal-oxide semiconductor (CMOS)-compatible silicon (Si) photonic chips, potentially containing integrated electronics, are disclosed. The integration techniques rely on light coupling with integrated light coupling elements such as turning mirrors, lenses, and surface grating couplers. Light is coupled from between two or more substrates using the light coupling elements. The technique can realize integrated lasers on Si where a gain flip chip (the second substrate) is bonded to a Si chip (the first substrate) and light is coupled between a waveguide in the gain flip chip to a Si waveguide by way of a turning mirror or grating coupler in the flip chip and a grating coupler in the Si chip. Integrated lenses and other elements such as spot-size converters can also be incorporated to alter the mode from the gain flip chip to enhance the coupling efficiency to the Si chip. The light coupling integration technique also allows for the integration of other components such as modulators, amplifiers, and photodetectors. These components can be waveguide-based or non-waveguide based, that is to say, surface emitting or illuminating.
19 Mar 2015
TL;DR: A hybrid integrated electrical-optical (E-O) interface including a driver/TIA chip in 28nm CMOS and a modulator/PD chip in SOI, based on a mixed-pitch bumping technology is presented, promising a disruptive alternative for next-generation scalable data centers.
Abstract: Integrated photonic interconnect technology is free from the bandwidth-distance limitation that intrinsically exists in electrical interconnects, promising a disruptive alternative for next-generation scalable data centers. Silicon photonic platforms have been reported based on monolithic and hybrid integration. Monolithic systems mitigate integration overhead but require compromise in either electronic or photonic device performance [1,2]. Hybrid integration allows for independent process selection for each device so that overall system can potentially achieve the best performance [3]. This paper presents a hybrid integrated electrical-optical (E-O) interface including a driver/TIA chip in 28nm CMOS and a modulator/PD chip in SOI, based on a mixed-pitch bumping technology. A pseudo-differential driver with pre-emphasis enables an 800MHz bandwidth (BW) carrier-injection ring modulator to operate at 25Gb/s with power efficiency of 2.9pJ/b. A TIA implements two BW-enhancement techniques: a regulated-cascode (RGC) input stage with shunt-shunt feedback and T-coil inductive peaking, and a hybrid offset calibration, achieving 25Gb/s with power efficiency of 2.0pJ/b and a sensitivity of −8.0dBm OMA.
Patent•
12 Mar 2015TL;DR: In this article, a semiconductor device includes a chip main body, a first layer that is provided on the chip's main body and contains nickel and phosphorus; and a second layer, which is the second layer of the device, which has a higher phosphorus concentration than the first layer.
Abstract: According to one exemplary embodiment, a semiconductor device includes a chip main body; a first layer that is provided on the chip main body and contains nickel and phosphorus; and a second layer that is provided on the first layer and contains nickel and phosphorus and has a higher phosphorus concentration than that of the first layer.
9 Mar 2015
TL;DR: This paper answers the question of whether a static signal can become the target of choice for actual adversaries, especially since it has smaller amplitude than its dynamic counterpart, based on actual measurements taken from an AES S-box prototype chip implemented in a 65-nanometer CMOS technology.
Abstract: Static power consumption is an increasingly important concern when designing circuits in deep submicron technologies. Besides its impact for low-power implementations, recent research has investigated whether it could lead to exploitable side-channel leakages. Both simulated analyses and measurements from FPGA devices have confirmed that such a static signal can indeed lead to successful key recoveries. In this respect, the main remaining question is whether it can become the target of choice for actual adversaries, especially since it has smaller amplitude than its dynamic counterpart. In this paper, we answer this question based on actual measurements taken from an AES S-box prototype chip implemented in a 65-nanometer CMOS technology. For this purpose, we first provide a fair comparison of the static and dynamic leakages in a univariate setting, based on worst-case information theoretic analysis. This comparison confirms that the static signal is significantly less informative than the dynamic one. Next, we extend our evaluations to a multivariate setting. In this case, we observe that simple averaging strategies can be used to reduce the noise in static leakage traces. As a result, we mainly conclude that (a) if the target chip is working at maximum clock frequency (which prevents the previously mentioned averaging), the static leakage signal remains substantially smaller than the dynamic one, so has limited impact, and (b) if the adversary can reduce the clock frequency, the noise of the static leakage traces can be reduced arbitrarily. Whether the static signal leads to more informative leakages than the dynamic one then depends on the quality of the measurements (as the former one has very small amplitude). But it anyway raises a warning flag for the implementation of algorithmic countermeasures such as masking, that require high noise levels.
Patent•
16 Feb 2015
TL;DR: In this article, a microelectronic assembly can include a substrate having first and second surfaces, at least two logic chips overlying the first surface, and a memory chip having a front surface with contacts thereon, the front surface of the memory chip confronting a rear surface of each logic chip.
Abstract: A microelectronic assembly can include a substrate having first and second surfaces, at least two logic chips overlying the first surface, and a memory chip having a front surface with contacts thereon, the front surface of the memory chip confronting a rear surface of each logic chip. The substrate can have conductive structure thereon and terminals exposed at the second surface for connection with a component. Signal contacts of each logic chip can be directly electrically connected to signal contacts of the other logic chips through the conductive structure of the substrate for transfer of signals between the logic chips. The logic chips can be adapted to simultaneously execute a set of instructions of a given thread of a process. The contacts of the memory chip can be directly electrically connected to the signal contacts of at least one of the logic chips through the conductive structure of the substrate.
Patent•
18 Aug 2015
TL;DR: In this article, the authors describe a transmission line driver system which is comprised of multiple paralleled driver elements, allowing efficient generation of multiple output signal levels with adjustable output amplitude, optionally including Finite Impulse Response signal shaping and skew pre-compensation.
Abstract: Transmission line driver systems are described which are comprised of multiple paralleled driver elements. The paralleled structure allows efficient generation of multiple output signal levels with adjustable output amplitude, optionally including Finite Impulse Response signal shaping and skew pre-compensation.
TL;DR: This paper presents the first silicon-proven stochastic LDPC decoder to support multiple code rates for IEEE 802.15.3c applications and achieves over 90% reduction of routing wires, 73.8% and 11.5% enhancement of hardware and energy efficiency, respectively.
Abstract: This paper presents the first silicon-proven stochastic LDPC decoder to support multiple code rates for IEEE 802.15.3c applications. The critical path is improved by a reconfigurable stochastic check node unit (CNU) and variable node unit (VNU); therefore, a high throughput scheme can be realized with 768 MHz clock frequency. To achieve higher hardware and energy efficiency, the reduced complexity architecture of tracking forecast memory is experimentally investigated to implement the variable node units for IEEE 802.15.3c applications. Based on the properties of parity check matrices and stochastic arithmetic, the optimized routing networks with re-permutation techniques are adopted to enhance chip utilization. Considering the measurement uncertainties, a delay-lock loop with isolated power domain and a test environment consisting of an encoder, an AWGN generator and bypass circuits are also designed for inner clock and information generation. With these features, our proposed fully parallel LDPC decoder chip fabricated in 90-nm CMOS process with 760.3 K gate count can achieve 7.92 Gb/s data rate and power consumption of 437.2 mW under 1.2 V supply voltage. Compared to the state-of-the-art IEEE 802.15.3c LDPC decoder chips, our proposed chip achieves over 90% reduction of routing wires, 73.8% and 11.5% enhancement of hardware and energy efficiency, respectively.
TL;DR: In this paper, the first time-bin entanglement photonic chip that integrates timebin generation, wavelength demultiplexing, and analysis is presented. But the chip is based on a silicon nitride photonic circuit, which combines the low-loss characteristic of silica and tight integration features of silicon, paves the way for scalable realworld quantum information processors.
Abstract: Photonic chip based time-bin entanglement has attracted significant attention because of its potential for quantum communication and computation. Useful time-bin entanglement systems must be able to generate, manipulate and analyze entangled photons on a photonic chip for stable, scalable and reconfigurable operation. Here we report the first time-bin entanglement photonic chip that integrates time-bin generation, wavelength demultiplexing and entanglement analysis. A two-photon interference fringe with an 88.4% visibility is measured (without subtracting any noise), indicating the high performance of the chip. Our approach, based on a silicon nitride photonic circuit, which combines the low-loss characteristic of silica and tight integration features of silicon, paves the way for scalable real-world quantum information processors.
Patent•
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16 Sep 2015
TL;DR: In this paper, a head-mounted display consisting of a first conversion chip, a first processing chip and a second processing chip is used to convert a video signal in input audio and video source signals into an RGB signal and output the RGB signal to the first processor.
Abstract: The invention discloses a head-mounted display. The head-mounted display comprises a first conversion chip, a first processing chip, a second conversion chip and a second processing chip; the first conversion chip is used to convert a video signal in input audio and video source signals into an RGB signal and output the RGB signal to the first processing chip, and is used to convert an audio signal in the input audio and video source signals into an I2S signal and output the I2S signal to the second processing chip; the first processing chip is used to perform optical processing on the input RGB signal and output the processed RGB signal to the second conversion chip; the second conversion chip is used to convert the input RGB signal after the optical processing into a preset interface signal and output the preset interface signal to a display screen interface of the head-mounted display; and the second processing chip is used to perform decoding processing on the input I2S signal and output the processed I2S signal to an earphone interface of the head-mounted display According to the scheme, the audio and video signals can respectively be adapted to the display screen interface and the earphone interface of the head-mounted display and then be output, and perfect visual experience and perfect auditory experience are provided for a user.
TL;DR: A miniaturized portable ultrasonic imager that uses a custom ASIC and a piezoelectric transducer array to transmit and capture 2-D sonographs that can image human tissue as deep as 5 cm while consuming less than 16.5 μJ per pulse-echo measurement.
Abstract: We present a miniaturized portable ultrasonic imager that uses a custom ASIC and a piezoelectric transducer array to transmit and capture 2-D sonographs. The ASIC, fabricated in 0.18 $\mu$ m 32 V CMOS process, contains 7 identical channels, each with high-voltage level-shifters, high-voltage DC-DC converters, digital TX beamformer, and RX front-end. The chip is powered by a single 1.8 V supply and generates 5 V and 32 V internally using on-chip charge pumps with an efficiency of 33% to provide 32 V pulses for driving a bulk piezoelectric transducer array. The assembled prototype can operate up to 40 MHz, with beamformer delay resolution of 5 ns, and has a measured sensitivity of 225 nV/Pa , minimum detectable signal of 622 Pa assuming 12 dB SNR ( $4\sigma$ larger than the noise level), and data acquisition time of 21.3 ms. The system can image human tissue as deep as 5 cm while consuming less than 16.5 $\mu$ J per pulse-echo measurement. The high energy efficiency of the imager can enable a number of consumer applications.
TL;DR: In this article, a single source of entangled photons is used to observe quantum interference on the same chip, which removes the need for clumsy interfacing of multiple photon sources, and provides a basis for highly scalable photonic circuits that achieve multi-qubit entanglement.
Abstract: Silicon photonics is a promising platform to realize the dense and scalable integration required for quantum computing, communication, and sensing. The authors demonstrate a key building block for this platform, a simple, single source of entangled photons, and use it to observe quantum interference on the same chip. This removes the need for clumsy interfacing of multiple photon sources, as in previous studies, and provides a basis for highly scalable photonic circuits that achieve multi-qubit entanglement.
19 Mar 2015
TL;DR: By using the proposed VDD-controlled oscillator (VDDCO), the frequency of which is controlled by varying its supply voltage, a hitherto unexplored feature of the multiphase DC-DC architecture is exposed: the control-loop unity gain frequency (UGF) could be designed to be higher than the switching frequency.
Abstract: Inspired by The Square of Vatican City, a fully integrated step-down switched-capacitor DC-DC converter ring with 100+ phases is designed with a fast dynamic voltage scaling (DVS) feature for the microprocessor in portable or wearable devices. As shown in Fig. 20.4.1, this symmetrical ring-shaped converter surrounds its load in the square and supplies the on-chip power grid, such that a good quality power supply can be easily accessed at any point of the chip edges. There are 30 phases on the top edge and 31 phases on each of the other 3 edges, making 123 phases in total. The phase number and unit cell dimensions of this architecture can easily be adjusted to fit the floor plan of the load. The pads of the converter-ring are placed at the corners, and will not affect the pads of the load. Moreover, by using the proposed V DD -controlled oscillator (V DD CO), the frequency of which is controlled by varying its supply voltage, a hitherto unexplored feature of the multiphase DC-DC architecture is exposed: the control-loop unity gain frequency (UGF) could be designed to be higher than the switching frequency.
TL;DR: In this article, the feasibility of P-i-N diode chip temperature extraction for a high-power module is investigated and the limitations of using forward voltage drop for high power P-n diode TSEP are explored.
Abstract: P-i-N diode chip temperature is a significant indicator when evaluating the reliability of high-power converters. The feasibility of state-of-the-art thermosensitive electrical parameter (TSEP) extraction strategies for a high-power module is investigated and the limitations of using forward voltage drop for high-power P-i-N diode TSEP are explored. In the widely employed half-bridge topology, by detailed analysis of the upper antiparallel diode reverse recovery process due to lower nonideal insulated-gate bipolar transistor switching behavior, the inherent monotonic relationship between the maximum recovery current rate di
d
/dt and chip temperature is disclosed. The maximum di
d
/dt during the recovery period is chosen as the better TSEP, which can accurately reflect P-i-N diode chip temperature variation. Fortunately, by monitoring the negative peak voltage on the parasitic inductor between the Kelvin and power emitters under different temperatures, the maximum recovery rate di
d
/dt can be readily determined. Consequently, additional passive components are not required for P-i-N diode chip temperature extraction, which is practical and cost-effective for high-power applications. Finally, a dynamic switching characteristics test platform based on a half-bridge topology is designed and adopted to experimentally verify the theoretical analysis. The experimental results show that the dependence between P-i-N diode chip temperature and the maximum recovery di
d
/dt is approximately linear. This leads to a 3-D lookup table that can be used to estimate online P-i-N diode chip temperature.
TL;DR: A novel multiple access scheme for M2M communications based on the capacity-approaching analog fountain code to efficiently minimize the access delay and satisfy the delay requirement for each device is proposed.
Abstract: Future machine to machine (M2M) communications need to support a massive number of devices communicating with each other with little or no human intervention. Random access techniques were originally proposed to enable M2M multiple access, but suffer from severe congestion and access delay in an M2M system with a large number of devices. In this paper, we propose a novel multiple access scheme for M2M communications based on the capacity-approaching analog fountain code to efficiently minimize the access delay and satisfy the delay requirement for each device. This is achieved by allowing M2M devices to transmit at the same time on the same channel in an optimal probabilistic manner based on their individual delay requirements. Simulation results show that the proposed scheme achieves a near optimal rate performance and at the same time guarantees the delay requirements of the devices. We further propose a simple random access strategy and characterized the required overhead. Simulation results show the proposed approach significantly outperforms the existing random access schemes currently used in long term evolution advanced (LTE-A) standard in terms of the access delay.
2 Nov 2015
TL;DR: A full optical chip-to-chip link is demonstrated for the first time in a wafer-scale heterogeneous platform, where the photonics and CMOS chips are 3D integrated using wafer bonding and low-parasitic capacitance thru-oxide vias (TOVs).
Abstract: A full optical chip-to-chip link is demonstrated for the first time in a wafer-scale heterogeneous platform, where the photonics and CMOS chips are 3D integrated using wafer bonding and low-parasitic capacitance thru-oxide vias (TOVs). This development platform yields 1000s of functional photonic components as well as 16M transistors per chip module. The transmitter operates at 6Gb/s with an energy cost of 100fJ/bit and the receiver at 7Gb/s with a sensitivity of 26μA (-14.5dBm) and 340fJ/bit energy consumption. A full 5Gb/s chip-to-chip link, with the on-chip calibration and self-test, is demonstrated over a 100m single mode optical fiber with 560fJ/bit of electrical and 4.2pJ/bit of optical energy. Keywords—optics; link; heterogeneous; 3D integration; transceivers;
Patent•
24 Jul 2015
TL;DR: In this paper, a super-chip is attached to multiple plain chips by long direct connections such as bond wires (e.g., BVAs) or solder stacks; such connections can be placed side by side with the super chip.
Abstract: In a multi-chip module (MCM), a “super” chip ( 110 N) is attached to multiple “plain” chips ( 110 F′ “super” and “plain” chips can be any chips). The super chip is positioned above the wiring board (WB) but below at least some of plain chips ( 110 F). The plain chips overlap the super chip. Further, the plain chips' low speed IOs can be connected to the WB by long direct connections such as bond wires (e.g. BVAs) or solder stacks; such connections can be placed side by side with the super chip. Such connections can be long, so the super chip is not required to be thin. Also, if through-substrate vias (TSVs) are omitted, the manufacturing yield is high and the manufacturing cost is low. Other structures are provided that combine the short and long direct connections to obtain desired physical and electrical properties.
TL;DR: This paper proposes passive and semi-passive wireless temperature and humidity sensors based on electronic product code (EPC) global Class-1 Generation-2 UHF communication protocol that can operate without battery power (passive mode) and also can co-operate with the off-chip temperature and moisture sensors powered by battery (semi-passIVE mode).
Abstract: This paper proposes passive and semi-passive wireless temperature and humidity sensors based on electronic product code (EPC) global Class-1 Generation-2 UHF communication protocol. The wireless sensors consist of a sensor key chip and off-chip temperature and humidity sensors. The sensor key chip integrates RF/analog front-end circuit, digital baseband processor, nonvolatile memory, on-chip temperature sensor, and sensor interface. The sensor interface connects the off-chip sensors and the sensor key chip. The sensor key chip with the on-chip temperature sensor can operate without battery power (passive mode), and also can co-operate with the off-chip temperature and humidity sensors powered by battery (semi-passive mode). The RF/analog front-end circuit provides the dc power to the sensor key chip and communicates with the interrogator passively. Advanced low-power techniques are adopted to reduce the power consumption of the sensor key chip. The sensor key chip is fabricated in 0.18- $\mu $ m CMOS process. In passive mode, the maximum wireless sensitivity of on-chip sensor is −15.1/−11.2 dBm for reading and sensing operation, respectively, and the temperature sensing error is −1 °C/0.8 °C over operating range from −20 °C to 50 °C. It achieves a reading/sensing distance of over 9.5/6 m with 4-W effective isotropic radiated power (EIRP) by the commercial interrogator. In semi-passive mode, the temperature and humidity sensing distance of off-chip sensors is 2.7 m.
22 Apr 2015
TL;DR: The issues of design flow for TMR flip-flops are investigated, addressing both the issues of compliance to the standard ASIC design methodology, enabling the use of non-modified RTL code, as well as the layout generation of radhard TMR flips, based on standard non-hardened Flip-flop components.
Abstract: Protection against radiation effects in digital ASICs chip can be achieved using different design approaches. One of the popular approaches for increasing the reliability is the hardware triplication. However, the hardware triplication does not mean that the susceptibility to radiation effects can be automatically overcome. The automatic random placement of standard cells can result in higher power consumption and more occupied silicon area), with marginal improvement of the linear energy transfer threshold (LET) value. Additionally, the TMR approach usually requires changes in the standard ASIC design flow, even requesting significant modifications of the RTL code. In this paper, we will investigate the issues of design flow for TMR flip-flops, addressing both the issues of compliance to the standard ASIC design methodology, enabling the use of non-modified RTL code, as well as the layout generation of radhard TMR flip-flops, based on standard non-hardened flip-flop components.
Patent•
6 Jan 2015
TL;DR: In this paper, a chip package and a method for forming the same are provided, which includes: providing a first chip, where the first chip comprises a first surface and a second surface, and a first plurality of pads are disposed on the first surface; providing a second chip, wherein the second surface comprises a third and a fourth surface, a second plurality of padding are disposed in the third surface; combining the second surfaces of the first and the third surfaces of second chips; and forming a first insulation layer, wherein insulation layer covers first chip and is combined with the second chip
Abstract: A chip package and a method for forming the same are provided. The method includes: providing a first chip, wherein the first chip comprises a first surface and a second surface, and a first plurality of pads are disposed on the first surface; providing a second chip, wherein the second chip comprises a third surface and a fourth surface, a second plurality of pads are disposed on the third surface; combining the second surface of the first chip and the third surface of the second chip, wherein the second plurality of pads are out of the combination area of the first chip and the second chip; and forming a first insulation layer, wherein the first insulation layer covers the first chip, and is combined with the second chip. Processes of the method are simple, and the chip package is small.
TL;DR: A 0.35 μm BiCMOS silicon chip that quantitatively models fundamental molecular circuits via efficient log-domain cytomorphic transistor equivalents is described and published static and dynamic MATLAB models of synthetic biological circuits including repressilators, feed-forward loops, and feedback oscillators are in excellent quantitative agreement with those from transistor circuits on the chip.
Abstract: We describe a $0.35~\mu{\rm m}$ BiCMOS silicon chip that quantitatively models fundamental molecular circuits via efficient log-domain cytomorphic transistor equivalents. These circuits include those for biochemical binding with automatic representation of non-modular and loading behavior, e.g., in cascade and fan-out topologies; for representing variable Hill-coefficient operation and cooperative binding; for representing inducer, transcription-factor, and DNA binding; for probabilistic gene transcription with analogic representations of log-linear and saturating operation; for gain, degradation, and dynamics of mRNA and protein variables in transcription and translation; and, for faithfully representing biological noise via tunable stochastic transistor circuits. The use of on-chip DACs and ADCs enables multiple chips to interact via incoming and outgoing molecular digital data packets and thus create scalable biochemical reaction networks. The use of off-chip digital processors and on-chip digital memory enables programmable connectivity and parameter storage. We show that published static and dynamic MATLAB models of synthetic biological circuits including repressilators, feed-forward loops, and feedback oscillators are in excellent quantitative agreement with those from transistor circuits on the chip. Computationally intensive stochastic Gillespie simulations of molecular production are also rapidly reproduced by the chip and can be reliably tuned over the range of signal-to-noise ratios observed in biological cells.