Abstract: The Timepix3, hybrid pixel detector (HPD) readout chip, a successor to the Timepix \cite{timepix2007} chip, can record time-of-arrival (ToA) and time-over-threshold (ToT) simultaneously in each pixel. ToA information is recorded in a 14-bit register at 40 MHz and can be refined by a further 4 bits with a nominal resolution of 1.5625 ns (640 MHz). ToT is recorded in a 10-bit overflow controlled counter at 40 MHz. Pixels can be programmed to record 14 bits of integral ToT and 10 bits of event counting, both at 40 MHz. The chip is designed in 130 nm CMOS and contains 256 × 256 pixel channels (55 × 55 μm2). The chip, which has more than 170 M transistors, has been conceived as a general-purpose readout chip for HPDs used in a wide range of applications. Common requirements of these applications are operation without a trigger signal, and sparse readout where only pixels containing event information are read out. A new architecture has been designed for sparse readout and can achieve a throughput of up to 40 Mhits/s/cm2. The flexible architecture offers readout schemes ranging from serial (one link) readout (40 Mbps) to faster parallel (up to 8 links) readout of 5.12 Gbps. In the ToA/ToT operation mode, readout is simultaneous with data acquisition thus keeping pixels sensitive at all times. The pixel matrix is formed by super pixel (SP) structures of 2 × 4 pixels. This optimizes resources by sharing the pixel readout logic which transports data from SPs to End-of-Column (EoC) using a 2-phase handshake protocol. To reduce power consumption in applications with a low duty cycle, an on-chip power pulsing scheme has been implemented. The logic switches bias currents of the analog front-ends in a sequential manner, and all front-ends can be switched in 800 ns. The digital design uses a mixture of commercial and custom standard cell libraries and was verified using Open Verification Methodology (OVM) and commercial timing analysis tools. The analog front-end and a voltage-controlled oscillator for 1.5625 ns timing resolution have been designed using full custom techniques.

Abstract: Increasing demand for higher-bandwidth DRAM drive TSV technology development. With the capacity of fine-pitch wide I/O [1], DRAM can be directly integrated on the interposer or host chip and communicate with the memory controller. However, there are many limitations, such as reliability and testability, in developing the technology. It is advantageous to adopt a logic-interface chip between the interposer and stacked-DRAM with thousands of TSV. The logic interface chip in the base level of high-bandwidth memory (HBM) decreases the CIO, repairs the chip-to-chip connection failure, and supports better testability and improves reliability.

Abstract: A vertically stacked image sensor having a photodiode chip and a transistor array chip The photodiode chip includes at least one photodiode and a transfer gate extends vertically from a top surface of the photodiode chip The image sensor further includes a transistor array chip stacked on top of the photodiode chip The transistor array chip includes the control circuitry and storage nodes The image sensor further includes a logic chip vertically stacked on the transistor array chip The transfer gate communicates data from the at least one photodiode to the transistor array chip and the logic chip selectively activates the vertical transfer gate, the reset gate, the source follower gate, and the row select gate

Abstract: Apparatus, and methods of manufacture thereof, in which metal is deposited into openings, thus forming a plurality of metal pads, a plurality of through-silicon-vias (TSVs), a plurality of metal lines, a plurality of first dummy structures, and a plurality of second dummy structures. Ones of the plurality of first dummy structures each have a first width that is at least about three times greater than a second width of each of the plurality of metal lines, and ones of the plurality of second dummy structures each have a third width that is at least about five times greater than the second width of each of the plurality of metal lines.

Abstract: This paper presents a complete 256-electrode retinal prosthesis chip, which is small and ready for packaging and implantation. It contains 256 separate programmable drivers dedicated to 256 electrodes for flexible stimulation. A 4-wire interface is employed for power and data transmission between the chip and a driving unit. Power and forward data are recovered from a 600 kHz differential signal, while backward data are sent at 100 kbps rate simultaneously. The stimulator possesses many stimulation features, supporting various stimulation strategies. Many safety features are included such as real-time monitoring of voltage compliance and temperature, electrode self-locking in the event of out-of-compliance, and ESD protection circuit at every electrode. The chip is fabricated in a 65 nm CMOS process. The electrode driver pitch is 150 μm, and total chip area is 8 mm 2 . The chip has been extensively tested and all the requirements have been successfully verified. The measured DC current error for single driver stimulation without electrode shorting is 20 nA. The average power consumption per electrode with typical stimulus pulse parameters and full-scale output current is 129 μW, inclusive of all standby power. The chip overall power efficiency is 70% with 23 mW of power delivered to load.

Abstract: An SiGe transmit-receive phased-array chip has been developed for automotive radar applications at 76-84 GHz. The chip is based on an all-RF beamforming approach and contains 8-transmit channels, 8-receive channels, and a complete built-in-self-test system. Two high-linearity quadrature mixers with an input P1 dB of +2.5 dBm are used and allow simultaneous sum and difference patterns in the receive mode. The chip operates in either a narrowband frequency-modulated continuous-wave (FMCW) mode or a wideband mode with > 2-GHz bandwidth. A high-linearity design results in an input P1 dB of -10 dBm (per channel), a system noise figure of 16-18 dB, and a transmit power is 4-5 dBm (per channel). The chip uses a controlled collapse chip connection (C4) bumping process and is flip-chipped on a low-cost printed-circuit board, and results in > 50-dB isolation between the transmit and receive chains. To our knowledge, this work represents the state-of-the-art in terms of complexity at millimeter-wave frequencies and with simultaneous transmit and receive operation for high-performance FMCW radars.

Abstract: We present a hybrid analog/digital very large scale integration (VLSI) implementation of a spiking neural network with programmable synaptic weights. The synaptic weight values are stored in an asynchronous Static Random Access Memory (SRAM) module, which is interfaced to a fast current-mode event-driven DAC for producing synaptic currents with the appropriate amplitude values. These currents are further integrated by current-mode integrator synapses to produce biophysically realistic temporal dynamics. The synapse output currents are then integrated by compact and efficient integrate and fire silicon neuron circuits with spike-frequency adaptation and adjustable refractory period and spike-reset voltage settings. The fabricated chip comprises a total of 32 × 32 SRAM cells, 4 × 32 synapse circuits and 32 × 1 silicon neurons. It acts as a transceiver, receiving asynchronous events in input, performing neural computation with hybrid analog/digital circuits on the input spikes, and eventually producing digital asynchronous events in output. Input, output, and synaptic weight values are transmitted to/from the chip using a common communication protocol based on the Address Event Representation (AER). Using this representation it is possible to interface the device to a workstation or a micro-controller and explore the effect of different types of Spike-Timing Dependent Plasticity (STDP) learning algorithms for updating the synaptic weights values in the SRAM module. We present experimental results demonstrating the correct operation of all the circuits present on the chip.

Abstract: The majority of the power consumption of a high-throughput LDPC decoder is spent on memory. Unlike in a general-purpose processor, the memory access in an LDPC decoder is deterministic and the access window is short. We take advantage of the unique memory access characteristic to design a non-refresh eDRAM that holds data for the necessary access window, and further improve its access time by trading off the excess retention time. The resulting 3T eDRAM cell is designed to balance wordline coupling to reliably retain data for a fast access. We integrate 32 5x210 non-refresh eDRAM arrays in a row-parallel LDPC decoder suitable for the IEEE 802.11ad standard. Memory refresh is eliminated and random access is replaced with a simple sequential addressing. With row merging and dual-frame processing, the 1.6 mm 2 65 nm LDPC decoder chip achieves a peak throughput of 9 Gb/s at 89.5 pJ/b, of which only 21% is spent on eDRAMs. With voltage and frequency scaling, the power consumption of the LDPC decoder is reduced to 37.7 mW for a 1.5 Gb/s throughput at 35.6 pJ/b.

Abstract: This work presents a single- and dual-port fully integrated millimeter-wave ultra-broadband vector network analyzer. Both circuits, realized in a commercial 0.35-μm SiGe:C technology with an ft/fmax of 170/250 GHz, cover an octave frequency bandwidth between 50-100 GHz. The presented chips can be configured to measure complex scattering parameters of external devices or determine the permittivity of different materials using an integrated millimeter-wave dielectric sensor. Both devices are based on a heterodyne architecture that achieves a receiver dynamic range of 57-72.5 dB over the complete design frequency range. Two integrated frequency synthesizer modules are included in each chip that enable the generation of the required test and local-oscillator millimeter-wave signals. A measurement 3σ statistical phase error lower than 0.3 ° is achieved. Automated measurement of changes in the dielectric properties of different materials is demonstrated using the proposed systems. The single- and dual-port network analyzer chips have a current consumption of 600 and 700 mA, respectively, drawn from a single 3.3-V supply.

Abstract: Voltage noise characterization is an essential aspect of optimizing the shipped voltage of high-end processor based systems. Voltage noise, i.e. Variations in the supply voltage due to transient fluctuations on current, can negatively affect the robustness of the design if it is not properly characterized. Modeling and estimation of voltage noise in a pre-silicon setting is typically inadequate because it is difficult to model the chip/system packaging and power distribution network (PDN) parameters very precisely. Therefore, a systematic, direct measurement-based characterization of voltage noise in a post-silicon setting is mandatory in validating the robustness of the design. In this paper, we present a direct measurement-based voltage noise characterization of a state-of-the-art mainframe class multicoreprocessor. We develop a systematic methodology to generate noise stress marks. We study the sensitivity of noise in relation to the different parameters involved in noise generation: (a) stimulus sequence frequency, (b) supply current delta, (c) number of noise events and, (d) degree of alignment or synchronization of events in a multi-core context. By sensing per-core noise in amulti-core chip, we characterize the noise propagation across the cores. This insight opens up new opportunities for noise mitigation via workload mappings and dynamic voltage guard banding.

Abstract: We present design and measurement details for a 0-3 multi-stage noise-shaping (MASH) ADC that achieves a dynamic range of 88 dB over 53 MHz signal bandwidth The ADC utilizes a zeroth-order front-end, ie, a 17-level flash ADC, to perform a coarse quantization and a third-order 7-level continuous-time ΔΣ back-end to digitize the residue error of the front-end The ADC achieves the high thermal noise power efficiency of a continuous-time feedforward ΔΣ modulator and the flat signal transfer function of a flash ADC The test chip, implemented in a 28 nm CMOS process, clocks at 32 GHz The average noise spectral density with small input signals is -167 dBFS/Hz and the dynamic range is 88 dB The test chip ADC consumes a total power of 235 mW from triple power supplies of 09/18/-10 V The thermal-noise figure-of-merit, defined as FOM = DR + 10log 10 (BW/P) is 1716 dB

Abstract: High Efficiency Video Coding, the latest video standard, uses larger and variable-sized coding units and longer interpolation filters than H.264/AVC to better exploit redundancy in video signals. These algorithmic techniques enable a 50% decrease in bitrate at the cost of computational complexity, external memory bandwidth, and, for ASIC implementations, on-chip SRAM of the video codec. This paper describes architectural optimizations for an HEVC video decoder chip. The chip uses a two-stage subpipelining scheme to reduce on-chip SRAM by 56 kbytes-a 32% reduction. A high-throughput read-only cache combined with DRAM-latency-aware memory mapping reduces DRAM bandwidth by 67%. The chip is built for HEVC Working Draft 4 Low Complexity configuration and occupies 1.77 mm2 in 40-nm CMOS. It performs 4K Ultra HD 30-fps video decoding at 200 MHz while consuming 1.19 nJ/pixel of normalized system power.

Abstract: Combining integrated circuitry with microfluidics enables lab-on-a-chip (LOC) devices to perform sensing, freeing them from benchtop equipment. However, this integration is challenging with small chips, as is briefly reviewed with reference to key metrics for package comparison. In this paper we present a simple packaging method for including mm-sized, foundry-fabricated dies containing complementary metal oxide semiconductor (CMOS) circuits within LOCs. The chip is embedded in an epoxy handle wafer to yield a level, large-area surface, allowing subsequent photolithographic post-processing and microfluidic integration. Electrical connection off-chip is provided by thin film metal traces passivated with parylene-C. The parylene is patterned to selectively expose the active sensing area of the chip, allowing direct interaction with a fluidic environment. The method accommodates any die size and automatically levels the die and handle wafer surfaces. Functionality was demonstrated by packaging two different types of CMOS sensor ICs, a bioamplifier chip with an array of surface electrodes connected to internal amplifiers for recording extracellular electrical signals and a capacitance sensor chip for monitoring cell adhesion and viability. Cells were cultured on the surface of both types of chips, and data were acquired using a PC. Long term culture (weeks) showed the packaging materials to be biocompatible. Package lifetime was demonstrated by exposure to fluids over a longer duration (months), and the package was robust enough to allow repeated sterilization and re-use. The ease of fabrication and good performance of this packaging method should allow wide adoption, thereby spurring advances in miniaturized sensing systems.

Abstract: We present a portable, battery-operated and application-specific lab-on-a-chip (ASLOC) system that can be easily configured for a wide range of lab-on-a-chip applications. It is based on multiplexed electrical current detection that serves as the sensing system. We demonstrate different configurations to perform most detection schemes currently in use in LOC systems, including some of the most advanced such as nanowire-based biosensing, surface plasmon resonance sensing, electrochemical detection and real-time PCR. The complete system is controlled by a single chip and the collected information is stored in situ, with the option of transferring the data to an external display by using a USB interface. In addition to providing a framework for truly portable real-life developments of LOC systems, we envisage that this system will have a significant impact on education, especially since it can easily demonstrate the benefits of integrated microanalytical systems.

Abstract: Systems and methods are described for transmitting data over physical channels to provide a high bandwidth, low latency interface between integrated circuit chips with low power utilization Communication is performed using group signaling over multiple wires using a vector signaling code, where each wire carries a low-swing signal that may take on more than two signal values

Abstract: A Multi-Service Optical Code Division Multiple Access (MS-OCDMA) code based on Spectral Amplitude Coding (SAC) is proposed in this paper. The advantage of proposed code on setting a variable number of users in a basic code matrix with a fixed code weight makes it more flexible in generating codewords. The appropriate quality of service required for various network applications can be provided by choosing a different number of users for the basic code matrix of MS code. The properties of the proposed code is compared with other OCDMA codes in terms of code length and maximum cross-correlation. The performance of the MS code mathematically analysed and probability of error for users is plotted as a function of the number of active users and optical received power. Shot, phase induced intensity and thermal noises are considered in mathematical analysis. Results show that by choosing code weight of 4 and optimizing number of users per sequence, the MS code supports up to 82 users, each operating at a bit-rate of 622 Mbps with reference to the Bit Error Rate (BER) of 10−9.

Abstract: Chip formation, an important aspect of the high-speed cutting (HSC) mechanism, is generally accepted as the result of shear deformation in the shear zone and tool-chip friction. In order to accurately study chip formation process in HSC, a theoretical model for the high-speed orthogonal cutting of aluminum alloy 6061-T6 was built, which can be used to calculate the important parameters of chip formation, such as shear angle, friction angle, length of shear plane, tool-chip contact length, and width of the first shear zone. A series of orthogonal cutting experiments, with the YG6 carbide tool and on a wide range of cutting speed (100–1,900 m/min) and feed (0.06–0.15 mm/r), were performed in order to obtain the parameters required in the model, including the cutting forces, the chip thickness, and the shear slip distance. Seven kinds of chip formation parameters were obtained with different cutting parameters in the experiment, and the built theoretical model can well explain the formation process and the morphology characteristics of these chips, which proves that the combined method of theoretical model and orthogonal cutting experiment is an effective and easy approach to obtain the parameters of chip formation in HSC, avoiding the cutting speed limitation and the safety risk in quick-stop test. Within the range of parameters set in the experiments, the chip mainly appears to be continuous chip, curling chip, or discontinuous chip. And the chip thickness, friction angle, length of shear plane, and width of the first shear zone decrease with the increase of the cutting speed; meanwhile, the shear slide distance and shear angle increase.

Abstract: Disclosed is a semiconductor device that is capable of handling multiple different high-frequency contactless communication modes and that is formed by a multi-chip structure. A first semiconductor chip, which performs interface control of high-frequency contactless communication and data processing of communications data, is mounted on a wiring board; and a second semiconductor chip, which performs another data processing of the communication data, is mounted on the first semiconductor chip. In this case, transmission pads in the first semiconductor chip are arranged at positions farther from a periphery of the chip than those of receiving pads, and the second semiconductor chip is mounted by being biased on the first semiconductor chip so as to keep away the transmission pads.

Abstract: The scalability trends of modern semiconductor technology lead to increasingly dense multicore chips. Unfortunately, physical limitations in area, power, off-chip bandwidth, and yield constrain single-chip designs to a relatively small number of cores, beyond which scaling becomes impractical. Multi-chip designs overcome these constraints, and can reach scales impossible to realize with conventional single-chip architectures. However, to deliver commensurate performance, multi-chip architectures require a cross-chip interconnect with bandwidth, latency, and energy consumption well beyond the reach of electrical signaling. We propose Galaxy, an architecture that enables the construction of a many-core "virtual chip" by connecting multiple smaller chiplets through optical fibers. The low optical loss of fibers allows the flexible placement of chiplets, and offers simpler packaging, power, and heat requirements. At the same time, the low latency and high bandwidth density of optical signaling maintain the tight coupling of cores, allowing the virtual chip to match the performance of a single chip that is not subject to area, power, and bandwidth limitations. Our results indicate that Galaxy attains speedup of 2.2x over the best single-chip alternatives with electrical or photonic interconnects (3.4x maximum), and 2.6x smaller energy-delay product (6.8x maximum). We show that Galaxy scales to 4K cores and attains 2.5x speedup at 6x lower laser power compared to a Macrochip with silicon waveguides.

Abstract: Next-generation high-performance computing systems require high-bandwidth serial links to transport high-speed data streams among computational blocks. Optical links have recently attracted attention due to their low channel loss at high frequencies, requiring simpler equalization circuits than electrical links. The energy-efficiency of optical links can thus be significantly improved [1-5]. Broadband techniques such as inductive peaking are commonly used in highspeed optical transceivers for bandwidth enhancement at the expense of the chip area. Inductor-less receivers have been proposed [4,6] to reduce chip area but they usually consume more power or have lower data rates at given technology nodes. In this paper, we present two optical receivers that each consists of a pseudodifferential CMOS push-pull transimpedance amplifier (TIA), a DC offset-cancellation circuit, a limiting amplifier (LA) with interleaving active-feedback [6], and a T-Coil fT-doubler output buffer. The block diagram and experimental setup are shown in Fig. 8.4.1. The capacitance of the off-chip GaAs PIN photodetector (PD), which is wire-bonded to the CMOS receiver, is 100fF with 0.4A/W responsivity. The two optical receivers have identical designs except for the LA, in which two different inductive peaking techniques, conventional and shared-inductor, are designed and fabricated on the same die in 28nm CMOS technology.

Abstract: A static random access memory (SRAM) chip including a plurality of SRAM cells and a plurality of cell current tracking cells. Each of the SRAM cells include a source voltage reference conductor, a first ground reference conductor, two cross-coupled inverters, and two pass-gate devices. Each cell current tracking cell include a first half-cell and a second half-cell. The first half-cell is different from the second half-cell.

Abstract: This study demonstrates that by combining a modified version of the Berthelot method with microfluidic technologies and LED based optical detection systems, a low cost monitoring system for detection of ammonia in fresh water and wastewater can be developed. The assay developed is a variation on the Berthelot method, eliminating several steps previously associated with the method to create a nontoxic and simple colorimetric assay. The previous Berthelot method required the addition of three reagents, mixed sequentially with the sample, which complicates the microfluidic system design. With the modified method, comparable results were attained using a single reagent addition step at a 1 : 1 v/v reagent to sample ratio, which significantly simplifies the fluidic handling requirement for integration into an autonomous sensing platform. The intense colour generated in the presence of ammonia is detected at a wavelength of 660 nm. The method allows for ammonia determination up to 12 mg L−1 NH4+ with a limit of detection of 0.015 mg L−1 NH4+. Validation was achieved by analysing split water samples by the modified method and by ion chromatography, resulting in an excellent correlation coefficient of 0.9954. The method was then implemented into a fully integrated sensing platform consisting of a sample inlet with filter, storage units for the Berthelot reagent and standards for self-calibration, pumping system which controls the transport and mixing of the sample, a microfluidic mixing and detection chip, and waste storage. The optical detection system consists of a LED light source with a photodiode detector, which enables sensitive detection of the coloured complex formed. The robustness and low cost of the microfluidic platform coupled with integrated wireless communications makes it an ideal platform for in situ environmental monitoring. This is the first demonstration of a fully functional microfluidic platform employing this modified version of the Berthelot method.

Abstract: Systems and methods are described for transmitting data over physical channels to provide a high speed, low latency interface such as between a memory controller and memory devices with significantly reduced or eliminated Simultaneous Switching Output noise. Controller-side and memory-side embodiments of such channel interfaces are disclosed which do not require additional pin count or data transfer cycles, have low power utilization, and introduce minimal additional latency. In some embodiments of the invention, three or more voltage levels are used for signaling.

Abstract: Chip sorting devices and methods of ejecting chips from chip wells are disclosed. In some embodiments, chip sorting devices may include at least one chip ejection unit including at least one finger member selectively movable between a first position outside of at least one channel of a chip conveying unit and a second position within the at least one channel. In additional embodiments, a chip sorting device may include a separating wheel comprising a plurality of chip wells, each chip well configured to hold a plurality of chips. In yet additional embodiments, methods of ejecting a chip from a chip well may include urging a selected chip out of the chip well with the at least one finger member and at least one wall segment of a trailing segmented wall of the chip well.

Abstract: Directly modulated semiconductor lasers are widely used, compact light sources in optical communications. Semiconductors can also be used to generate nonclassical light; in fact, CMOS-compatible silicon chips can be used to generate pairs of single photons at room temperature. Unlike the classical laser, the photon-pair source requires control over a two-dimensional joint spectral intensity (JSI) and it is not possible to process the photons separately, as this could destroy the entanglement. Here we design a photon-pair source, consisting of planar lightwave components fabricated using CMOS-compatible lithography in silicon, which has the capability to vary the JSI. By controlling either the optical pump wavelength, or the temperature of the chip, we demonstrate the ability to select different JSIs, with a large variation in the Schmidt number. Such control can benefit high-dimensional communications where detector-timing constraints can be relaxed by realizing a large Schmidt number in a small frequency range. The controlled creation of single and pair photon sources on a silicon chip is important for the realisation of quantum optical communications. Here, the authors control the spectrum of such photons generated on a silicon chip.

Abstract: This paper presents a 10-bit column driver IC for active-matrix LCDs, with a proposed iterative charge-sharing based (ICSB) capacitor-string that interpolates two output voltages from a resistor-string DAC. Iterative mode change between a capacitive voltage division mode and a charge sharing mode in the ICSB capacitor-string interpolation suppresses the effect of mismatches between capacitors and that of parasitic capacitances; thus, a highly linear capacitor sub-DAC is realized. In addition, the area-sharing layout technique, which stacks the interpolation capacitor-string on top of the R-DAC area, reduces the driver channel size and extends the bit resolution of the gamma-corrected nonlinear main R-DAC. Consequently, the proposed ICSB capacitor-string interpolation scheme provides highly uniform channel performance by passively dividing the coarse voltages from the global resistor-string DAC with high area efficiency, and more effective bit resolution for nonlinear gamma correction. The prototype column driver IC was implemented using a 0.11-μm CMOS process. The area occupation of the DAC and buffer amplifier per channel is only 188 × 15 μm2, and the static power consumption is 0.9 μA/channel with no additional static power dissipation for the interpolation. The measured maximum DNL and INL are 0.25 LSB and 0.43 LSB, respectively. The measured maximum inter-channel DVO is 5.6 mV. The proposed chip achieves state-of-the-art performance in terms of chip size and channel-to-channel uniformity.

Abstract: This paper presents the development and demonstration of a high-efficiency rectifier for millimeter-wave-to-dc energy conversion. It is a critical circuit block that renders possible the use of a single CMOS chip die with no substrate and wiring, as the implementation of a batteryless, yet active tag for next-generation high data-rate millimeter-wave identification technologies. We also propose an architecture of a reader-tag system that addresses the underlying technical challenges. The rectifier is based on a differential drive cross-coupled topology that has been shown to work at UHF frequencies only so far. In this paper, we investigate significant challenges in implementing this topology at millimeter-wave frequencies with good power conversion efficiency (PCE). The analyses, design, and results presented in this work demonstrate the feasibility of achieving this by minimizing simultaneously the small on-resistance and the reverse leakage current in the MOS transistors, and by reducing losses and parasitic capacitances through proper transistor sizing and layout optimization. Using a standard 65-nm bulk CMOS process, a chip was designed, fabricated, and tested under different input and output loading conditions. The rectifier exhibits an overall PCE of 20% at 24 GHz, 18% at 35 GHz, and 11% at 60 GHz under RF available driving power of 6, 6, and 3 dBm, respectively, and output load resistance of 1, 1, and 2 kΩ, respectively. These PCE performances at millimeter-wave frequencies have never been reported in the literature.