Abstract: A CMOS type semiconductor image sensor module wherein a pixel aperture ratio is improved, chip use efficiency is improved and furthermore, simultaneous shutter operation by all the pixels is made possible, and a method for manufacturing such semiconductor image sensor module are provided. The semiconductor image sensor module is provided by stacking a first semiconductor chip, which has an image sensor wherein a plurality of pixels composed of a photoelectric conversion element and a transistor are arranged, and a second semiconductor chip, which has an A/D converter array. Preferably, the semiconductor image sensor module is provided by stacking a third semiconductor chip having a memory element array. Furthermore, the semiconductor image sensor module is provided by stacking the first semiconductor chip having the image sensor and a fourth semiconductor chip having an analog nonvolatile memory array.

Abstract: In micromachining, the uncut chip thickness is comparable or even less than the tool edge radius and as a result a chip will not be generated if the uncut chip thickness is less than a critical value, viz., the minimum chip thickness. The minimum chip thickness effect significantly affects machining process performance in terms of cutting forces, tool wear, surface integrity, process stability, etc. In this paper, an analytical model has been developed to predict the minimum chip thickness values, which are critical for the process model development and process planning and optimization. The model accounts for the effects of thermal softening and strain hardening on the minimum chip thickness. The influence of cutting velocity and tool edge radius on the minimum chip thickness has been taken into account. The model has been experimentally validated with 1040 steel and A16082-T6 over a range of cutting velocities and tool edge radii. The developed model has then been applied to investigate the effects of cutting velocity and edge radius on the normalized minimum chip thickness for various carbon steels with different carbon contents and A16082-T6.

Abstract: In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.

Abstract: The chip for the multi-chip semiconductor device having the markings for alignment formed on the front surface and/or the back surface of the chip only by the processing from the front surface of the chip (photolithography, etch) and the method for manufacturing same are presented, without adding any dedicated process step to the formation process for the marking for alignment. In the chip for the multi-chip semiconductor device having two or more electroconductive through plug in one chip for the multi-chip semiconductor device, one or more electroconductive through plugs are employed for the marking for alignment, and the chip is configured to allow identification of the marking for alignment on the front surface and/or the back surface of the chip for the multi-chip semiconductor device. Then, an insulating film is provided on the front surface and/or the back surface of the electrically conducting through plug.

Abstract: As the reliability is a critical issue for new generation multi-level cell (MLC) flash memories, there is growing call for fast and compact error correction code (ECC) circuit with minimum impact on memory access time and chip area. This paper presents a high-throughput and low-power ECC scheme for MLC NAND flash memories. The BCH encoder and decoder architecture features byte-wise processing and a low complexity key equation solver using a simplified Berlekamp-Massey algorithm. Resource sharing and power reduction techniques are also applied. Synthesized using 0.25-mum CMOS technology in a supply voltage of 2.5 V, the proposed BCH (4148,4096) encoder/decoder achieves byte-wise processing, and it needs an estimated cell area of 0.2 mm2, and an average power of 3.18 mW with 50 MB/s throughput

Abstract: This paper presents a fully electronic label-free DNA chip in 0.5-mum CMOS technology, with 5-V supply voltage, suitable for low-cost highly integrated applications. The chip features an array of 128 sensor sites with gold electrodes and integrated measurement, conditioning, multiplexing and analog-to-digital conversion circuitry. The circuits measure capacitance variations due to DNA hybridization on the gold electrodes which are bio-modified by covalently attaching probes of known sequence. Specificity, repeatability and parallel detection capability of the fabricated chip are successfully demonstrated

Abstract: An energy-efficient network-on-chip (NoC) is presented for possible application to high-performance system-on-chip (SoC) design. It incorporates heterogeneous intellectual properties (IPs) such as multiple RISCs and SRAMs, a reconfigurable logic array, an off-chip gateway, and a 1.6-GHz phase-locked loop (PLL). Its hierarchically-star-connected on-chip network provides the integrated IPs, which operate at different clock frequencies, with packet-switched serial-communication infrastructure. Various low-power techniques such as low-swing signaling, partially activated crossbar, serial link coding, and clock frequency scaling are devised, and applied to achieve the power-efficient on-chip communications. The 5 /spl times/5 mm/sup 2/ chip containing all the above features is fabricated by 0.18-/spl mu/m CMOS process and successfully measured and demonstrated on a system evaluation board where multimedia applications run. The fabricated chip can deliver 11.2-GB/s aggregated bandwidth at 1.6-GHz signaling frequency. The chip consumes 160 mW and the on-chip network dissipates less than 51 mW.

Abstract: This paper presents a single-chip pulse generator developed for Ultra Wide Band (UWB) wireless communication systems based on impulse radio technology. The chip has been integrated in a CMOS 130-nm technology with a single supply voltage of 1.2 V. The basic concept is to combine different delayed edges in order to form a very short duration "logical" pulse, and then filter it, so as to obtain an UWB pulse. It is possible to vary the output pulse shape, and thus the corresponding spectrum, just by acting on the delayed edge combination. Furthermore, the pulse generator supports both position modulation (2-PPM) and polarity modulation (BPSK modulation) in order to convey data through the air. Its power consumption remains less than 10 mW for a raw data rate of up to 160 Mb/s. Spectral and temporal measurements of the single-chip pulse generator are presented with an illustration of the modulation effects on the power spectral density (PSD)

Abstract: A single chromatin immunoprecipitation (ChIP) sample does not provide enough DNA for hybridization to a genomic tiling array. A commonly used technique for amplifying the DNA obtained from ChIP assays is ligation-mediated PCR (LM-PCR). However; using this amplification method, we could not identify Oct4 binding sites on genomic tiling arrays representing 1% of the human genome (ENCODE arrays). In contrast, hybridization of a pool of 10 ChIP samples to the arrays produced reproducible binding patterns and low background signals. However the pooling method would greatly increase the number of ChIP reactions needed to analyze the entire human genome. Therefore, we have adapted the GenomePlex whole genome amplification (WGA) method for use in ChIP-chip assays; detailed ChIP and amplification protocols used for these analyses are provided as supplementary material. When applied to ENCODE arrays, the products prepared using this new method resulted in an Oct4 binding pattern similar to that from the pooled Oct4 ChIP samples. Importantly, the signal-to-noise ratio using the GenomePlex WGA method is superior to the LM-PCR amplification method.

Abstract: A signaling system is disclosed. The signaling system includes a first integrated circuit (IC) chip to receive a data signal and a strobe signal. The first IC includes circuitry to sample the data signal at times indicated by the strobe signal to generate phase error information and circuitry to output the phase error information from the first IC device. The system further includes a signaling link and a second IC chip coupled to the first IC chip via the signaling link to output the data signal and the strobe signal to the first IC chip. The second IC chip includes delay circuitry to generate the strobe signal by delaying an aperiodic timing signal for a first time interval and timing control circuitry to receive the phase error information from the first IC chip and adjust the first time interval in accordance with the phase error information.

Abstract: An energy-efficient network-on-chip (NoC) is pre- sented for possible application to high-performance system-on- chip (SoC) design. It incorporates heterogeneous intellectual prop- erties (IPs) such as multiple RISCs and SRAMs, a reconfigurable logic array, an off-chip gateway, and a 1.6-GHz phase-locked loop (PLL). Its hierarchically-star-connected on-chip network provides the integrated IPs, which operate at different clock frequencies, with packet-switched serial-communication infrastructure. Var- ious low-power techniques such as low-swing signaling, partially activated crossbar, serial link coding, and clock frequency scaling are devised, and applied to achieve the power-efficient on-chip communications. The 5 5m m chip containing all the above features is fabricated by 0.18- m CMOS process and successfully measured and demonstrated on a system evaluation board where multimedia applications run. The fabricated chip can deliver 11.2-GB/s aggregated bandwidth at 1.6-GHz signaling frequency. The chip consumes 160 mW and the on-chip network dissipates less than 51 mW.

Abstract: Direct-sequence (DS) code-division multiple access (CDMA) is considered for future wideband mobile underwater acoustic networks, where a typical configuration may include several autonomous underwater vehicles (AUVs) operating within a few kilometers of a central receiver. Two receivers that utilize multichannel (array) processing of asynchronous multiuser signals are proposed: the symbol decision feedback (SDF) receiver and the chip hypothesis feedback (CHF) receiver. Both receivers use a chip-resolution adaptive front end consisting of a many-to-few combiner and a bank of fractionally-spaced feedforward equalizers. In the SDF receiver, feedback equalization is implemented at symbol resolution, and receiver filters, including a decision-directed phase-locked loop, are adapted at the symbol rate. This limits its applicability to the channels whose time variation is slow compared to the symbol rate. In a wideband acoustic system, which transmits at maximal chip rate, the symbol rate is down-scaled by the spreading factor, and an inverse effect may occur by which increasing the spreading factor results in performance degradation. To eliminate this effect, feedback equalization, which is necessary for the majority of acoustic channels, is performed in the CHF receiver at chip resolution and receiver parameters are adjusted at the chip rate. At the price of increased computational complexity (there are as many adaptive filters as there are symbol values), this receiver provides improved performance for systems where time variation cannot be neglected with respect to the symbol rate [e.g., low probability of detection (LPD) acoustic systems]. Performance of the two receivers was demonstrated in a four-user scenario, using experimental data obtained over a 2-km shallow-water channel. At the chip rate of 19.2 kilochips per second (kc/s) with quaternary phase-shift keying (QPSK) modulation, excellent results were achieved at an aggregate data rate of up to 10 kb/s

Abstract: A method and apparatus for an ultra-high sensitivity, low cost, passive (no battery) low-power energy harvesting data transmitting circuit energy, such as a RFID (Radio Frequency IDentification) tag integrated circuit 'chip.' By using combinations of special purpose design enhancements, the low-power energy harvesting passive data transmitting circuit, such as the RFID tag chip, operates in the sub-microwatt power range. The chip power should be derived from a low-microwatt per square centimeter RF field radiated to the RFID tag antenna from the tag reader (interrogator) or derived from a suitable low signal source, such as a sonic transducer (e.g., a piezoelectric transducer or a low level DC source, such as a bi-metallic or chemical source).

Abstract: A method of coordinating resources for repetition of random access bursts performed by a mobile terminal, the method comprising: determining groups of access slots based on parameters from a network, wherein each access slot is defined by any combination of frequency, time and code, and the access slots are organized according to a frequency pattern; transmitting an access burst on an access slot from a chosen group of access slots; and re-transmitting the access burst on the next access slot from the chosen group of access slots.

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device capable of preventing leakage of memory data from a signal exposed on the upper part. SOLUTION: The semiconductor integrated circuit device, in which a plurality of packages 102, 104, 106, 108 are laminated, is provided with a security chip 107, a security cover 110 attached on the laminated packages 102, 104, 106, 108, and data protection wiring 110 for security signal transmission. The security chip 107 transmits a signal to the data protection wiring 110, and compares a signal returned through the data protection wiring 110 with the original signal. Then, on the basis of the comparison result, elements in the plurality of packages 102, 104, 106, 108 are deactivated. COPYRIGHT: (C)2007,JPO&INPIT

Abstract: A novel solid-state biosensor for label-free detection of DNA hybridization is presented. The new device is realized in a standard CMOS process, thus allowing the realization of low-cost, portable, fully integrated devices. The detection mechanism is based on the field-effect of the intrinsic negative electric charge of DNA molecules which modulates the threshold voltage of a floating-gate MOS transistor. A fluid cell was developed for delivering DNA samples on the active surface of the chip. The device has an integrated, individual counter-electrode, so dry measurements are possible increasing lifetime of the chip and speeding up the experiment. Successful measurements on a first prototype of the chip, hosting 16 sensors individually addressable, are provided as proof of concept.

Abstract: We report on inter-chip bidirectional communication and power transfer between two stacked chips. The experimental prototype system components were fabricated in a 0.5-mum silicon-on-sapphire CMOS technology. Bi-directional communication between the two chips is experimentally measured at 1Hz-15 MHz. The circuits on the floating top chip are powered with capacitively coupled energy using a charge pump. This is the first demonstration of simultaneous nongalvanic power and data transfer between chips in a stack. The potential use in 3-D VLSI is aimed at reducing costs and complexity that are associated with galvanic inter-chip vias in 3-D integration

Abstract: A high dynamic range CMOS image sensor with inpixel light-to-frequency conversion has been designed. The prototype chip was fabricated in a standard 0.18-mum single-poly six-metal CMOS technology. The experimental results show that, operating at 1.2 V, the sensor can achieve a linear dynamic range of over 115 dB and an overall dynamic range of over 130 dB

Abstract: Issues related to substrate noise in system-on- chip design are described including the physical phenomena responsible for its creation, coupling transmission mechanisms and media, parameters affecting coupling strength, and its impact on mixed-signal integrated circuits. Design guidelines and best practices to minimize the generation, transmission, and reception of substrate noise are outlined, and different modeling approaches and computer simulation methods used in quantifying the noise coupling phenomena are presented. Finally, experiments that validate the modeling approaches and mitigation techniques are reviewed.

Abstract: A 1Tb/s 3W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1GHz and data rate of 1Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30mum. The total layout area is 2mm2 in 0.18mum CMOS and the chip thickness is 10mum. 4-phase TDMA reduces crosstalk and the BER is <10minus;12. Bi-phase modulation is used to improve noise immunity, reducing power in the transceiver

Abstract: A semiconductor apparatus includes: a first insulating layer formed on an IC chip; a metal wiring having one end connected to a chip electrode pad, and one other end on which an external connection terminal mounting electrode is provided; an electronic component connected to part of the external connection terminal mounting electrode; an external connection terminal, which is made of a conductive material, formed on one other part of the external connection terminal mounting electrode; a second insulating layer covering, at least, (a) part of the external connection terminal mounting electrode to which the electronic component is not mounted, and (b) the metal wiring; and a sealing resin for sealing the electronic component and the external connection terminal in such a manner that the external connection terminal is partially exposed so as to have an exposed portion. Thus, a semiconductor apparatus and a manufacturing method thereof are provided, each of which realizes a wafer-level CSP on which an electronic component is mounted in such a manner that the electronic component is mounted on re-wiring, wherein the external connection terminal is (i) prevented from being deformed after mounted on the IC chip, from being decreased in height, and from being expanded to a horizontal direction; and (ii) formed with a fine pitch from another external connection terminal located adjacent from the external connection terminal, so that the wafer-level CSP is highly functional and has a large number of pins.

Abstract: Global on-chip data communication is becoming a concern as the gap between transistor speed and interconnect bandwidth increases with CMOS process scaling. Repeaters can partly bridge this gap, but the classical repeater insertion approach requires a large number of repeaters while the intrinsic data capacity of each interconnect-segment is only partially used. In this paper we analyze interconnects and show how a combination of layout, termination and equalization techniques can significantly increase the data rate for a given length of uninterrupted interconnect. To validate these techniques, a bus-transceiver test chip in a 0.13-μm, 1.2-V, 6-M copper CMOS process has been designed. The chip uses 10-mm-long differential interconnects with wire widths and spacing of only 0.4 μm. Differential interconnects are insensitive to common-mode disturbances (e.g., non-neighbor crosstalk) and enable the use of twists to mitigate neighbor-to-neighbor crosstalk. With transceivers operating in conventional mode, the chip achieves only 0.55 Gb/s/ch. The achievable data rate increases to 3 Gb/s/ch (consuming 2 pJ/bit) with a pulse-width pre-emphasis technique, used in combination with resistive termination.

Abstract: Global on-chip data communication is becoming a concern as the gap between transistor speed and interconnect bandwidth increases with CMOS process scaling. Repeaters can partly bridge this gap, but the classical repeater insertion approach requires a large number of repeaters while the intrinsic data capacity of each interconnect-segment is only partially used. In this paper we analyze interconnects and show how a combination of layout, termination and equalization techniques can significantly increase the data rate for a given length of uninterrupted interconnect. To validate these techniques, a bus-transceiver test chip in a 0.13-/spl mu/m, 1.2-V, 6-M copper CMOS process has been designed. The chip uses 10-mm-long differential interconnects with wire widths and spacing of only 0.4 /spl mu/m. Differential interconnects are insensitive to common-mode disturbances (e.g., non-neighbor crosstalk) and enable the use of twists to mitigate neighbor-to-neighbor crosstalk. With transceivers operating in conventional mode, the chip achieves only 0.55 Gb/s/ch. The achievable data rate increases to 3 Gb/s/ch (consuming 2 pJ/bit) with a pulse-width pre-emphasis technique, used in combination with resistive termination.

Abstract: A new three-dimensional (3D) integration technology using the chip-to-wafer bonding technique provides the ultimate super-chip integration in which various kinds of chip of different sizes can be vertically stacked and electrically connected through a number of vertical interconnections. We have investigated several key technologies of vertical interconnection formation, chip alignment, chip-to-wafer bonding, adhesive injection, and chip thinning to vertically stack known good dies (KGDs) into 3D LSI chips. By using these key technologies, successful fabrication of 3D LSI test chips with vertical interconnections consisting of In–Au microbumps and buried interconnections filled with polycrystalline silicon (poly-Si) was demonstrated. The test chips was composed of three kinds of very thin chip of 5, 6, and 7 mm2 and ranging in thickness from 30 to 90 µm. Each chip is tightly bonded using a low-viscosity epoxy adhesive as a dielectric material.

Abstract: Increasing demand for high-speed interchip interconnects requires faster links that consume less power. The Shannon limit for the capacity of these links is at least an order of magnitude higher than the data rate of the current state-of-the-art designs. Channel coding can be used to approach the theoretical Shannon limit. Although there are numerous capacity-approaching codes in the literature, the complexity of these codes prohibits their use in high-speed interchip applications. This work studies several suitable coding schemes for chip-to-chip communication and backplane application. These coding schemes achieve 3-dB coding gain in the case of an additive white Gaussian noise (AWGN) model for the channel. In addition, a more realistic model for the channel is developed here that takes into account the effect of crosstalk, jitter, reflection, inter-symbol interference (ISI), and AWGN. Interestingly, the proposed signaling schemes are significantly less sensitive to such interference. Simulation results show coding gains of 5-8 dB for these methods with three typical channel models. In addition, low-complexity decoding architectures for implementation of these schemes are presented. Finally, circuit simulation results confirm that the high-speed implementations of these methods are feasible.

Abstract: A transmitting apparatus comprises a switching means for switching wireless access methods; a frequency domain signal generating means for assigning a wireless resource to a spread chip sequence, which has been subjected to one of a fast Fourier transform process and a serial/parallel conversion process in accordance with a wireless access method as switched, to generate a frequency domain signal; and a transport signal generating means for performing an inverse fast Fourier transform of the frequency domain signal to generate a transport signal.

Abstract: A test chip has been built to study the effects of layout on the delay and leakage of digital circuits in 90nm CMOS. The delay is characterized through the spread of ring oscillator frequencies and the transistor leakage is measured by using an on-chip ADC

Abstract: An orthogonal frequency division multiplexing (OFDM)-code division multiple access (CDMA) system is disclosed. The system includes a transmitter and a receiver. At the transmitter, a spreading and subcarrier mapping unit spreads an input data symbol with a complex quadratic sequence code to generate a plurality of chips and maps each chip to one of a plurality of subcarriers. An inverse discrete Fourier transform is performed on the chips mapped to the subcarriers and a cyclic prefix (CP) is inserted to an OFDM frame. A parallel-to-serial converter converts the time-domain data into a serial data stream for transmission. At the receiver, a serial-to-parallel converter converts received data into multiple received data streams and the CP is removed from the received data. A discrete Fourier transform is performed on the received data streams and equalization is performed. A despreader despreads an output of the equalizer to recover the transmitted data.

Abstract: A CMOS image sensor/processor chip fabricated in a 0.35 /spl mu/m CMOS technology is presented. The chip contains a general purpose software-programmable SIMD array of 128/spl times/128 processing elements. It executes over 20 GOPS while dissipating 240 mW of power and achieves pixel-processor density of 410 cells/mm/sup 2/. Performance and accuracy measurement results are given.