Abstract: This paper presents the design and implementation of an advanced digital controller for a 1-kW H-bridge dc-dc power converter. A new control algorithm based on the active disturbance rejection concept is developed to cope with the highly nonlinear dynamics of the converter and the disturbances. An experimental digital control system is used to implement the new control strategy. It consists of a digital control board based on the TMS320C6711 digital signal processor chip, an analogy I/O board, and a complex programmable logic device pulsewidth-modulation generation board. Using a newly developed bandwidth-parametrization technique, an autotuning method based on noise quantification is also developed and tested. Experimental results show the advantages and flexibilities of the new control method for the H-bridge dc-dc power converter.

Abstract: System-on-Package (SOP) technology based on silicon carriers has the potential to provide modular design flexibility and high-performance integration of heterogeneous chip technologies and to support robust chip manufacturing with high-yield/low-cost chips for a wide range of two- and three-dimensional product applications. Key technology enablers include silicon through-vias, high-density wiring, high-I/O chip interconnection, and supporting test and assembly technologies. The silicon through-vias are a key feature permitting efficient area array signal, power, and ground interconnection through these thinned silicon packages. High-density wiring and high-density chip I/O interconnection can enable tight integration of heterogeneous chip technologies which approximate the performance of an integrated system-on-chip with a "virtual chip" using the silicon package for integration. Silicon carrier fabrication leverages existing manufacturing capability and mid-UV lithography to provide very dense package wiring following CMOS back-end-of-line design rules. Further, the thermal expansion of the silicon carrier package matches the chip, which helps maintain reliability even as the high-density chip microbump interconnections scale to smaller size. In addition to heterogeneous chip integration, SOP products may leverage the integration of passive components, active devices, and electro-optic structures to enhance system-level performance while also maintaining functional test capability and known good chips when needed. This paper describes the technical challenges and recent progress made in the development of silicon carrier technology for potential new applications.

Abstract: This work presents an intraprocess dynamic voltage and frequency scaling (DVFS) technique targeted toward nonreal-time applications running on an embedded system platform. The key idea is to make use of runtime information about the external memory access statistics in order to perform CPU voltage and frequency scaling with the goal of minimizing the energy consumption while translucently controlling the performance penalty. The proposed DVFS technique relies on dynamically constructed regression models that allow the CPU to calculate the expected workload and slack time for the next time slot and, thus, adjust its voltage and frequency in order to save energy, while meeting soft timing constraints. This is, in turn, achieved by estimating and exploiting the ratio of the total off-chip access time to the total on-chip computation time. The proposed technique has been implemented on an XScale-based embedded system platform and actual energy savings have been calculated by current measurements in hardware. For memory-bound programs, a CPU energy saving of more than 70% with a performance degradation of 12% was achieved. For CPU-bound programs, 15% /spl sim/ 60% CPU energy saving was achieved at the cost of 5%-20% performance penalty.

Abstract: A process of manufacturing a three-dimensional integrated circuit chip or wafer assembly and, more particularly, a processing of chips while arranged on a wafer prior to orienting the chips into stacks. Also disclosed is the manufacture of the three-dimensional integrated circuit wherein the chip density can be very high and processed while the wafers are still intact and generally of planar constructions.

Abstract: This paper presents a technique for characterizing the statistical properties and spectrum of power supply noise using only two on-chip low-throughput samplers. The samplers utilize a voltage-controlled oscillator to perform high-resolution analog-to-digital conversion with minimal hardware. The measurement system is implemented in a 0.13-/spl mu/m process along with a high-speed link transceiver. Measured results from this chip validate the accuracy of the measurement system and elucidate several aspects of power supply noise, including its cyclostationary nature.

Abstract: A time-to-digital-converter-based CMOS smart temperature sensor is proposed for high-accuracy portable applications. Conventional smart temperature sensors rely on an analog-to-digital converter, which consumes much chip area and operating power, for digital output code conversion. For the purpose of cost reduction and power saving, the proposed smart temperature sensor first generates a pulse with a width proportional to the measured temperature. Then, a cyclic time-to-digital converter (TDC) is utilized to convert the pulse into the corresponding digital code. The test chips, with extremely small area of 0.175 mm/sup 2/, were fabricated by the TSMC CMOS 0.35 /spl mu/m 2P4M process. Due to the excellent linearity of the digital output, the achieved measurement error is merely -0.6/spl deg/C to +0.8/spl deg/C without any curvature correction or dynamic offset-cancellation. The effective resolution is better than 0.15/spl deg/C, and the power consumption is 10 /spl mu/W.

Abstract: A method for designing semiconductor light emitting devices is disclosed wherein the side surfaces (surfaces not parallel to the epitaxial layers) are formed at preferred angles relative to vertical (normal to the plane of the light-emitting active layer) to improve light extraction efficiency and increase total light output efficiency. Device designs are chosen to improve efficiency without resorting to excessive active area-yield loss due to shaping. As such, these designs are suitable for low-cost, high-volume manufacturing of semiconductor light-emitting devices with improved characteristics.

Abstract: This paper describes the development and evaluation of a large transistor-based sensor array chip for direct extracellular imaging. All of the sensors and electronics are designed and fabricated using an unmodified CMOS process. The sensor array chip consists of a 16 × 16 pixel array of ISFETs along with signal acquisition and readout circuitry. Each ISFET employs a floating gate electrode structure and uses the passivation layer as a pH sensitive membrane. The chip layout is optimised so that the surface topography allows cultured cells to be grown directly above the pixel array. On return from the foundry, a double layer of SU-8 photoresist is used to provide a biocompatible and waterproof package for the chip. An elastomer-based microfluidic chamber is fabricated and integrated for conducting long term cell culture experiments. The performance of the chip is evaluated using an electrolyte and a well-established confluent cell line. The fabricated circuit provides a linear operating range of 2.5 V that allows each ISFET to operate as a pH sensor in the array. The ISFETs have a threshold voltage of − 1.5 V and a sensitivity of 46 mV/pH.

Abstract: This article outlines a multiple access scheme in which interleaving is the only means of user separation. As a special form of CDMA, the new scheme inherits many advantages of CDMA, such as dynamic channel sharing, mitigation of cross-cell interference, asynchronous transmission, ease of cell planning, and robustness against fading. Furthermore, it allows a low-cost interference cancellation technique applicable to systems with large numbers of users in multipath channels. Performance close to theoretical limits has been observed based on an unequal power control strategy.

Abstract: A wireless bus for stacked chips was developed by utilizing inductive coupling among them. This paper discusses inductor layout optimization and transceiver circuit design. The inductive coupling is analyzed by a simple equivalent circuit model, parameters of which are extracted by a magnetic field model based on the Biot-Savart law. Given communication distance, transmit power, data rate, and SNR budget, inductor layout size is minimized. Two receiver circuits, signal sensitive and yet noise immune, are designed for inductive nonreturn-to-zero (NRZ) signaling where no signal is transmitted when data remains the same. A test chip was fabricated in 0.35-/spl mu/m CMOS technology. Accuracy of the models is verified. Bit-error rate is investigated for various inductor layouts and communication distance. The maximum data rate is 1.25 Gb/s/channel. Power dissipation is 43 mW in the transmitter and 2.6 mW in the receiver at 3.3 V. If chip thickness is reduced to 30 /spl mu/m in 90-nm device generation, power dissipation will be 1 mW/channel or bandwidth will be 1 Tb/s/mm/sup 2/.

Abstract: An LED can include a silicon substrate and a pair of electrodes formed inside a horn that is formed on the silicon substrate by anisotropic etching. The LED can include an LED chip mounted inside the horn, the LED chip being electrically connected to the pair of electrodes. A resin mold made of a resin material can be filled in the horn.

Abstract: Real time artificial vision is traditionally limited to the frame rate. In many scenarios most frames contain information redundant both within and across frames. Here we report on the development of an Address-Event Representation (AER) [1] silicon retina chip `TMPDIFF’ that generates events corresponding to changes in log intensity. The resulting address-events are output asynchronously on a shared digital bus. This chip responds with high temporal and low spatial resolution, analogous to the biological magnocellular pathway. It has 64x64 pixels, each with 2 outputs (ON and OFF), which are communicated off-chip on a 13-bit digital bus. It is fabricated in a 0.35u 4M 2P process and occupies an area of (3.3 mm). Each (40u) pixel has 28 transistors and 3 capacitors and uses a self-clocked switched-capacitor design to limit response FPN. Dynamic operating range is at least 5 decades and minimum scene illumination with f/1.4 lens is less than 10 lux. Chip power consumption is 7mW.

Abstract: A compact slotted PIFA-type RFID tag (900 MHz) mountable on metallic objects is presented. The proposed structure can be easily matched to most microchips and facilitates their attachment on its slot. The performance of the tag is evaluated by monitoring its radar cross-sections (RCSs) for various incident angles and chip impedances. The measured detection distance is 4 m.

Abstract: Systems and methods are disclosed to dissipate heat from a semiconductor substrate. A package for integrated circuit includes a chip having a plurality of chip pads adapted to receive the variety of signals from or to output the same to an external circuit; a lead frame having a plurality of contact points each corresponding to a chip pad; and nano ceramic material in thermal communication with the chip for removing heat from the chip.

Abstract: Fast Fourier transform (FFT) processing is one of the key procedures in the popular orthogonal frequency division multiplexing (OFDM) communication systems. Structured pipeline architectures and low power consumption are the main concerns for its VLSI implementation. In the paper, the authors report a variable-length FFT processor design that is based on a radix-2/4/8 algorithm and a single-path delay feedback architecture. The processor can be used in various OFDM-based communication systems, such as digital audio broadcasting (DAB), digital video broadcasting-terrestrial (DVB-T), asymmetric digital subscriber loop (ADSL) and very-high-speed digital subscriber loop (VDSL). To reduce power consumption and chip area, special current-mode SRAMs are adopted to replace shift registers in the delay lines. In addition, techniques including complex multipliers containing three real multiplications, and reduced sine/cosine tables are adopted. The chip is fabricated using a 0.35 /spl mu/m CMOS process and it measures 3900 /spl mu/m /spl times/ 5500 /spl mu/m. According to the measured results, the 2048-point FFT operation can function correctly up to 45 MHz with a 3.3 V supply voltage and power consumption of 640 mW. In low-power operation, when the supply voltage is scaled down to 2.3 V, the processor consumes 176 mW when it runs at 17.8 MHz.

Abstract: To achieve ultimate super chip integration, we have developed a three-dimensional integration technology called super-smart-stack technology using a self-assembly technique The chip alignment accuracy of within 1mum is obtained by the self-assembly technique We demonstrated for the first time that 3D SRAM test chip with ten memory layers was successfully fabricated using the super-smart-stack (SSS) technology

Abstract: A 120-mV/sub ppd/ low swing pulse receiver is presented for AC coupled interconnect (ACCI). Using this receiver, 3Gb/s chip-to-chip communication is demonstrated through a wire-bonded ACCI channel with 150-fF coupling capacitors, across 15-cm FR4 microstrip lines. A test chip was fabricated in TSMC 0.18-/spl mu/m CMOS technology and the driver and pulse receiver dissipate 15-mW power per I/O at 3 Gb/s, with a bit error rate less than 10/sup -12/. First-time demonstration of a flip-chip ACCI is also presented, with both the AC and DC connections successfully integrated between the flipped chip and the multichip module (MCM) substrate by using the buried bump technology. For the flip-chip ACCI, 2.5 Gb/s/channel communication is demonstrated across 5.6 cm of transmission line on a MCM substrate.

Abstract: A radio frequency identification (RFID) device detection system includes an RFID device reader configured to detect RFID devices within a predetermined designated area, and two or more jamming signal transmitters configured to prevent the RFID device reader from detecting and reading devices outside of the designated area. The jamming signal transmitters may include a pair of low-frequency field generator loops driven out of phase with one another. RFID devices for use with the detection system may have a pair of antennas, one for detection by the RFID reading system, and another antenna for use in receiving signals from the jamming signal transmitters, in order to prevent communication with a wireless communication device such as an RFID chip, to which the antennas are coupled. The two antennas may be coupled to the RFID chip in parallel, with the antennas each coupled to the same contacts of the RFID chip.

Abstract: This article presents two approaches to solving the problem of communication between components dynamically placed at runtime on a reconfigurable device. The first is a circuit-routing approach designed for existing FPGAs. This approach uses the reconfigurable multiple bus (RMB). The second, network-based approach targets devices with unlimited reconfiguration capability such as coarse-grained reconfigurable devices. We introduce the dynamic network on chip (DyNoC) as a viable communication infrastructure for communication on dynamically reconfigurable devices. For prototyping the DyNoC on FPGAs, we design and implement an unrestricted communication model for a columnwise-reconfigurable chip. For the DyNoC, as well as for the RMB on chip (RMBoC), we provide algorithms and implementation results from real-life problems.

Abstract: The current technology in micro-and nano-electronics is insufficient to meet future demands for several applications. Most state-of-the-art solutions rely on so-called embedded technologies, which are both expensive and complex. One solution to the problem of integrating mixed technologies is the concept of 3D stacking. Our approach implements an epitaxial etch-stop layer for thickness control of the thinning process. Using this etch-stop layer, we can create a precise alignment of back-side vias to the landing pads in the first metal layer of the active CMOS, resulting in small via diameters and high connection densities between individual-layers of the 3D stack. Furthermore, we can use other materials, like GaAs (gallium arsenide), in combination with an epitaxial lift-off process. We use a copper-tin soldering process based on the solid-liquid interdiffusion (solid) process to create the electrical and mechanical connection between the single chip layers. Using this process, we created true multilayer stacks and tested them with respect to the static electrical properties of ohmic contacts and interchip vias. We directly incorporated these results in the design of test circuits that create tests for stuck-at failures of the interchip connections after stack assembly. This article presents a technology overview of how to achieve the goal in a 3D fabrication process. It also shows measurements for characterizing interconnects.

Abstract: A direct conversion receiver for UWB applications operates in 3.1-8.2 GHz and gives a NF of 3.3-4.1 dB and a conversion gain of 52 dB. The chip includes an RF receive chain and a 16 GHz quadrature VCO to generate seven carrier frequencies from 3.4 to 7.9 GHz. The circuit is fabricated in 0.18 /spl mu/m SiGe BiCMOS process and draws 88 mA from a 2.7 V supply.

Abstract: A liquid crystal display device including a liquid crystal display panel, a first driver circuit substrate, a second driver unit substrate and a flexible connector. The first driver circuit substrate provides electrical connection for at least one driver chip for the liquid crystal display panel with the first driver circuit being disposed at a peripheral portion of the liquid crystal display panel. The second driver circuit substrate has at least a connector to be connected with an external circuit with the second driver circuit substrate being disposed in superposed relation to at least a portion of the first driver circuit substrate. The flexible connector electrically connects at least a part of the first driver circuit substrate to at least a part of the second driver substrate.

Abstract: This paper presents program pulse characterization in an 8-Mb BJT-selected phase-change memory test chip. Experimental results of the impact of the bit-line resistance over programming pulse efficiency are provided. Furthermore, in order to compensate for spreads in cell physical parameters in an array portion, a non-conventional staircase-down program pulse is proposed and experimentally evaluated.

Abstract: The invention relates to a high power LED package, in which a package body is integrally formed with resin to have a recess for receiving an LED chip. A first sheet metal member is electrically connected with the LED chip, supports the LED chip at its upper partial portion in the recess, is surrounded by the package body extending to the side face of the package body, and has a heat transfer section for transferring heat generated from the LED chip to the metal plate of the board and extending downward from the inside of the package body so that a lower end thereof is exposed at a bottom face of the package body thus to contact the board. A second sheet metal member is electrically connected with the LED chip spaced apart from the first sheet metal member for a predetermined gap, and extends through the inside of the package body to the side face of the package body in a direction opposite to the first sheet metal member. A transparent sealant is sealingly filled up into the recess. The LED package raises thermal radiation efficiency with a simplified structure in order to reduce the size and thickness thereof.

Abstract: Duobinary signaling is combined with a proposed electrical pre-equalization scheme to extend the reach of 10-Gb/s signals that are transmitted over standard single-mode fiber. The proposed scheme is based on predistorting the duobinary signal using two T/2-spaced finite-impulse response (FIR) filters. The outputs of the FIR filters then modulate two optical carriers that are in phase quadrature. Simulation results show that distances in excess of 400 km at bit-error rates less than 10/sup -15/ are possible. Incorporating a forward-error correction scheme can extend the reach to distances in excess of 800 km. The reach limitation arises not from chromatic dispersion but from fiber nonlinearity, relative intensity noise due to phase-modulation-to-amplitude-modulation noise conversion, and optical amplifier noise accumulation. To demonstrate the feasibility of implementing the proposed scheme, a test chip is implemented in a 0.5-/spl mu/m SiGe BiCMOS technology. The chip incorporates two 10-tap T/2-spaced FIR filters, which are sufficient to equalize a 10-Gb/s duobinary signal that is transmitted over distances in excess of 400 km. The pre-equalization capabilities of the chip are tested by postprocessing the measured chip output to mimic the effects of the optical channel.

Abstract: A low-jitter 5000ppm spread-spectrum clock generator is implemented in a 0.18/spl mu/m CMOS process. By using 10 multi-phase clocks and a /spl Delta//spl Sigma/ modulator with periodic input, the chip has a deterministic jitter of 25ps due to spread-spectrum clocking and an amount of spreading of 5000ppm.

Abstract: A Fabry-Perot cavity filter includes a first mirror and a second mirror. A gap between the first and the second mirror monotonically varies as a function of width of the filter. This filter may be used with photodetector and a channel selection filter in an optical device, such as a spectrum analyzer. The channel selection filter may be a metal nanooptic filter array which includes plurality of subwavelength apertures in a metal film or between metal islands.