Abstract: Implanted sensors offer many advantages to those studying the behavior of the human body. Unfortunately, the need to power and communicate with devices often requires tradeoffs that compromise their usefulness. We describe a power harvesting and telemetry chip that allows operation without wires or batteries. The chip has been fabricated in 0.5 /spl mu/m CMOS. The chip is able to supply 2 mA at 33 V to associated sensors using inductive coupling. Tests reveal the characteristics of this chip under different loads and at different distances from the transmission coil. With the preliminary coils, functionality could be maintained with over 28 mm between the two coils. To evaluate the performance of the chip in conditions mimicking implantation in the body, water bearing colloids were introduced between the two coils. This resulted in a small loss of transfer efficiency, with no change in the behavior of the chip.

Abstract: This paper presents an intra-process dynamic voltage and frequency scaling (DVFS) technique targeted toward non real-time applications running on an embedded system platform. The key idea is to make use of runtime information about the external memory access statistics in order to perform CPU voltage and frequency scaling with the goal of minimizing the energy consumption while translucently controlling the performance penalty. The proposed DVFS technique relies on dynamically-constructed regression models that allow the CPU to calculate the expected workload and slack time for the next time slot, and thus, adjust its voltage and frequency in order to save energy while meeting soft timing constraints. This is in turn achieved by estimating and exploiting the ratio of the total off-chip access time to the total on-chip computation time. The proposed technique has been implemented on an XScale-based embedded system platform and actual energy savings have been calculated by current measurements in hardware. For memory-bound programs, a CPU energy saving of more than 70% with a performance degradation of 12% was achieved. For CPU-bound programs, 15/spl sim/60% CPU energy saving was achieved at the cost of 5-20% performance penalty.

Abstract: An intermediate chip for electrically connecting semiconductor chips includes: a substrate having a first side and a second side; a trans-substrate conductive plug which projects to the first side of the substrate; a post electrode which is displaced from the trans-substrate conductive plug in plan view on the second side of the substrate; and wiring which is disposed in or on the substrate for coupling the trans-substrate conductive plug and the post electrode.

Abstract: This paper presents a survey and classification of architectures for integrated circuit implementation of digital pulse-width modulators (DPWM) targeting digital control of high-frequency switching DC-DC power converters. Previously presented designs are identified as particular cases of the proposed classification. In order to optimize circuit resources in terms of occupied area and power consumption, a general architecture based on tapped delay lines is proposed, which includes segmentation of the input digital code to drive binary weighted delay cells and thermometer-decoded unary delay cells. Integrated circuit design of a particular example of the segmented DPWM is described. The segmented DPWM prototype chip operates at 1 MHz switching frequency and has low power consumption and very small silicon area (0.07 mm/sup 2/ in a standard 0.5 micron CMOS process). Experimental results validate the functionality of the proposed segmented DPWM.

Abstract: This paper reports results from wireless chip-to-chip communication experiments. Sixteen bit words pass from one chip to another in parallel without detectable error at 1.35 billion data items per second for a total data rate of 21.6 Gigabits per second. The experiment transmits pseudo random patterns between chips built in a 350-nm CMOS technology. Chips touch face-to-face to communicate. The same pseudorandom data pattern is loaded onto both chips so that the receiving chip can check the accuracy of every bit communicated. Each communication channel consumes a static power of 3.6 mW, and a dynamic power of 3.9 pJ per bit communicated. The channels lie on 50-/spl mu/m centers. Because the capacitive communication works through covering oxide, ESD protection is unnecessary. Vernier position measuring circuits built into the chips indicate the relative position of transmitting and receiving arrays to assist mechanical alignment. The test chip includes a Vernier measurement circuit that provides inter-chip position measurements with a resolution of 1.4 /spl mu/m.

Abstract: This paper discusses the development of an enhanced, static model of chip formation in micromilling processes that is able to describe the intermittency of the chip formation observed at low feeds per tooth due to the dominance of the minimum chip thickness effect. Experimental analyses demonstrate the validity of the proposed model by verifying the level of periodicity in the cutting forces present at various feeds per tooth. A key finding of this study is the identification of a local maximum in the radial thrust forces in the micromilling process during the noncutting regime, at feeds per tooth that are of the order of the minimum chip thickness. To overcome the challenges in the direct measurement of the minimum chip thickness, this paper presents a method for estimating the minimum chip thickness of various combinations of tools and workpiece materials based on easily attainable cutting-force data. A discussion on the selection of process parameters to avoid intermittent chip formation is also presented.

Abstract: A spread spectrum receiver processes signals from a plurality of sources modulated by different spread spectrum codes by sampling the signals as received to produce an integer series of sampling segments at a sampling rate at least twice a chip rate of the codes, each sampling segment containing an integer number of bits representing a fraction of a chip of the codes, time division multiplexing each sample segment into a number of channels, correlating the bits in each sample segment in each channel in parallel with a source specific series of locally generated sequential code samples differing by one bit, summing each parallel correlation, and accumulating the summed parallel correlations for each code sample in each channel at a rate at least equal to the chip rate to derive data related to each of the sources.

Abstract: A single chip protocol converter integrated circuit (IC) capable of receiving packets generating according to a first protocol type and processing said packets to implement protocol conversion and generating converted packets of a second protocol type for output thereof, the process of protocol conversion being performed entirely within the single integrated circuit chip. The single chip protocol converter can be further implemented as a macro core in a system-on-chip (SoC) implementation, wherein the process of protocol conversion is contained within a SoC protocol conversion macro core without requiring the processing resources of a host system. Packet conversion may additionally entail converting packets generated according to a first protocol version level and processing the said packets to implement protocol conversion for generating converted packets according to a second protocol version level, but within the same protocol family type. The single chip protocol converter integrated circuit and SoC protocol conversion macro implementation include multiprocessing capability including processor devices that are configurable to adapt and modify the operating functionality of the chip.

Abstract: A semiconductor integrated circuit device which requires high packaging density adopts a method for forming bumps in a terminal section of a semiconductor chip and bonding the semiconductor chip directly on a substrate. In this case, in order to prevent damage to the semiconductor integrated chip, which would otherwise be caused by bonding pressure employed at the time of bonding operation, non-connected dummy bumps are provided at corner sections of the semiconductor chip. Even when the dummy bumps are provided, there arises a necessity for preventing an increase in the size of the semiconductor chips, which would otherwise arise when the dummy bumps are provided on the chip.

Abstract: Mechanically and reversibly activating or deactivating a radio frequency identification (RFID) data tag. An RFID tag includes an RFID chip for storing an RFID code, an antenna for communicating a radio frequency (RF) signal, and a mechanical switch coupling the RFID chip to the antenna. Closing the mechanical switch enables the RFID chip and the antenna to communicate the RFID code via the RF signal.

Abstract: Conventional SIMD image processors are very effective for early visual processing because of their parallelism. However, in performing more advanced processing, they exhibit some problems, such as poor performance in global operations and a tradeoff between flexibility of processing and the number of pixels. This paper shows a new architecture and sample algorithms of a vision chip that has the ability to reconfigure its hardware dynamically by chaining processing elements. A prototype chip with 64/spl times/64 pixels manufactured using the 0.35-/spl mu/m CMOS process is also shown.

Abstract: We present an integrated multiple patch-clamp array chip by utilizing lateral cell trapping junctions. The intersectional design of a microfluidic network provides multiple cell addressing and manipulation sites for efficient electrophysiological measurements at a number of patch sites. The patch pores consist of openings in the sidewall of a main fluidic channel, and a membrane patch is drawn into a smaller horizontal channel. This device geometry not only minimizes capacitive coupling between the cell reservoir and the patch channel, but also allows simultaneous optical and electrical measurements of ion channel proteins. Evidence of the hydrodynamic placement of mammalian cells at the patch sites as well as measurements of patch sealing resistance is presented. Device fabrication is based on micromolding of polydimethylsiloxane, thus allowing inexpensive mass production of disposable high-throughput biochips.

Abstract: An RFID tag includes a dielectric member, an antenna pattern formed on and around a surface of the dielectric member, and an IC chip that is electrically connected to the antenna pattern by means of two chip pads.

Abstract: A multi-chips stacked package comprises a substrate, an upper chip, a lower chip, a dam, a heat spreader, an underfill, a plurality of first electrically conductive bumps and a plurality of second electrically conductive bumps. The upper chip is flip-chip bonded to the upper surface of the substrate and the second chip is accommodated in the opening and flip-chip bonded to the upper chip. Furthermore, the dam is disposed on the substrate and supports the heat spreader so as to fix the heat spreader to the back surface of the first chip. In addition, the underfill is filled into the space which is enclosed by the dam, the upper surface of the substrate and the heat spreader. In such a manner, at least the upper chip, the lower chip, the first and second electrically conductive bumps and a portion of the substrate are covered by the underfill. Thus, the underfill is connected to the dam, the heat spreader and the substrate simultaneously, so the reinforced structure including the heat spreader, the underfill and the dam can restrain the thermal deformation of the substrate and the upper chip and prevent the first electrically conductive bumps connecting the upper chip and the substrate from being damaged.

Abstract: For future large-scale integration design technology, the device matrix array (DMA), which precisely evaluates within-die variation in device parameters, has been developed. The DMA consists of a 14-by-14 array of common units. The unit size is 240 by 240 /spl mu/m, and each unit contains 148 measurement elements (52 transistors, 30 capacitors, 51 resistors, and 15 ring oscillators). The element selection and precise measurement are achieved with low parasitic resistance measurement buses and leakage-controlled switching circuits, which allow the measurement accuracy for a transistor, resistor, or capacitor of 90 pA, 11 m/spl Omega/, and 23 aF, respectively, in the 3/spl sigma/ range. The ability to obtain 29 008 samples from a chip enables statistical analysis of the variation in 148 elements of each chip with 240-/spl mu/m spatial resolution. This high resolution and large sample number allows us to precisely decompose the data into systematic and random variation parts with newly developed fourth-order polynomial fitting. Our methodology has been verified using a test chip fabricated by a 130-nm CMOS process with a 100-nm physical gate length and five Cu interconnect layers. In MOSFETs, the random part was dominant and indicated a certain /spl sigma/ value in every chip. In the case of the interconnect layers, the random and systematic parts of the resistance and the capacitance indicated variance fluctuations. By chip, by item, by size, by structure, random or systematic, the /spl sigma/ values of each variation show inconsistency which we believe is attributable to the Cu process. The correlation coefficients of systematic part between device element and ring oscillator frequency shown very high value (0.87-0.98), and those of a random part were low enough (-0.10-0.22) to prove the accuracy of decomposition.

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which has improved manufacturing yield and efficiency through improvement of wiring structure and also realized reduction in manufacturing cost even when a plurality of semiconductor chips are laminated. SOLUTION: A plurality of chip connecting wires 8 in which a plurality of semiconductor chips 2 including a plurality of terminals 5 are electrically connected to each terminal 5 are formed substantially in the same pattern. Moreover, the semiconductor chip is mounted at least one by one on the two sheets of chip mounting base material 6 which are laminated in two layers in the thickness direction. A sheet of wiring base material 15, in which a plurality of intermediate wires 17 electrically connected to each connecting wiring 8 are formed in the pattern which is different from that of each connecting wiring 8, is allocated between each mounting base material 6. Within a plurality of through-holes which are provided through each mounting base material 6 and wiring base material 15 in the laminating direction thereof, a plurality of interlayer connecting wires 30 are formed to electrically connect each connecting wiring 8 and each intermediate wiring 17 in the laminating direction of the base materials 6, 15. COPYRIGHT: (C)2004,JPO

Abstract: A stacked flip-chip package comprises a substrate having an opening, a back-to-face chip module, and an encapsulant. The back-to-face chip module is attached to the substrate and encapsulated by the encapsulant. The back-to-face chip module includes a first chip and a second chip. The first chip has a first active surface and a first back surface. Redistributed traces are formed on the first back surface. The second chip is flip-chip mounted on the first back surface of the first chip and electrically connected to the redistributed traces. A plurality of bumps connect the redistributed traces to the top surface of the substrate. Thus the second chip can be accommodated inside the opening and the redistributed traces are electrically connected to the second chip and the substrate so as to achieve fine pitch flip-chip mounting and improve the electrical performance and heat dissipation efficiency for the back-to-face chip module.

Abstract: A chip-to-chip communication system and interface technique. A master and at least two devices are interconnected with a signal line of a high speed bus. A capacitive coupling element, for example a diode, is employed to capacitively couple the interface of the device to the signal line. By employing the capacitive coupling element, along with a suitable signaling technique which supports capacitive information transfer, high speed rates of information transfer between the master and device over the signal line are achieved.

Abstract: A connection component for mounting a chip or other microelectronic element is formed from a starting unit including posts projecting from a dielectric element by crushing or otherwise reducing the height of at least some of the posts.

Abstract: This paper presents a mixed-signal programmable chip for high-speed vision applications. It consists of an array of processing elements, arranged to operate in accordance with the principles of single instruction multiple data (SIMD) computing architectures. This chip, implemented in a 0.35-/spl mu/m fully digital CMOS technology, contains /spl sim/ 3.75 M transistors and exhibits peak performance figures of 330 GOPS (8-bit equivalent giga-operations per second), 3.6 GOPS/mm/sup 2/ and 82.5 GOPS/W. It includes structures for image acquisition and for image processing, meaning that it does not require a separate imager for operation. At the sensory side, integration and log-compression sensing circuits are embedded, thus allowing the chip to handle a large variety of illumination conditions. At the processing plane, analog and digital circuits are employed whose parameters can be programmed and their architecture reconfigured for the realization of software-coded processing algorithms. The chip provides, and accepts, 8-bit digitized data through a 32-bit bidirectional data bus which operates at 120 MB/s. Experimental results show that frame rates of 1000 frames per second (FPS) can be achieved under room illumination conditions; applications using exposures of about 50 /spl mu/s have been recently reached by using special illumination setups. The chip can capture an image, run approximately 150 two-dimensional linear convolutions, and download the result in 8-bit digital format, in less than 1 ms. This feature, together with the possibility of executing sequences of user-definable instructions (stored on a full-custom 32-kb on-chip memory), and storing intermediate results (up to 8 grayscale images) makes the chip a true general-purpose sensory/processing device.

Abstract: The present invention provides a chip package structure and the manufacturing method thereof, which affords higher heat dissipation efficiency and is suitable to fabricate the stack type package structure with a higher integration The chip package structure comprises a carrier, at least a chip, a heat sink and a mold compound The chip is disposed on the carrier, while the bonding pads of the chip are electrically connected to the leads of the carrier The heat sink is disposed over the chip and includes at least a body and a plurality of connecting portions The connecting portions are disposed around a periphery of the body and are electrically connected to the leads By using a specially designed heat sink, the chip package structure can afford better heat dissipation and be suitable to form stack type package structures

Abstract: In some embodiments, the invention includes a chip having a register to include an operation type signal. The chip also includes control circuitry to receive a first command and in response to the first command to cause the chip to perform a first operation if the operation type signal has a first value and to cause the chip to perform a second operation if the operation type signal has a second value. The chip may be a memory chip in a memory system. Other embodiments are described and claimed.

Abstract: A fully integrated gas sensor microsystem is presented, which comprises for the first time a micro hot plate as well as advanced analog and digital circuitry on a single chip. The micro hot plate is coated with a nanocrystalline SnO2 thick film. The sensor chip is produced in an industrial 0.8-μm CMOS process with subsequent micromachining steps. A novel circular micro hot plate, which is 500 × 500 μm2 in size, features an excellent temperature homogeneity of ±2% over the heated area (300-μm diameter) and a high thermal efficiency of 6.0 °C/mW. A robust prototype package was developed, which relies on standard microelectronic packaging methods. Apart from a microcontroller board for managing chip communication and providing power supply and reference signals, no additional measurement equipment is needed. The on-chip digital temperature controller can accurately adjust the membrane temperature between 170 and 300 °C with an error of ±2 °C. The on-chip logarithmic converter covers a wide measurement range ...

Abstract: Through the use of an allocation logic unit with a Flash controller, a single primary chip enable is de-multiplexed into a multiple secondary chip enables for multiple Flash memory dies or chips. In so doing, Flash storage device capacity is greatly expanded. In a first aspect, a memory package includes a plurality of memories; and an allocation logic unit coupled to the plurality of memories for receiving a single chip enable signal. The allocation logic unit de-multiplexes the single chip enable signal to a plurality of chip enable signals. Each of the plurality of chip enable signals access to one of the plurality of memories. In a second aspect, a printed circuit board (PCB) includes a Flash controller for providing at least one primary chip enable signal. The PCB also includes a plurality of Flash memory chips and at least one allocation logic unit coupled to at least a portion of the plurality of Flash memory chips and the Flash controller. The allocation logic unit receives the at least one chip enable signal and de-multiplexes the at least one chip enable signal to a plurality of secondary chip enable signals. Each of the plurality of chip enable signals controls access to one of the Flash memory chips.

Abstract: The present invention relates to a multi-chip package structure, comprising a first substrate, a first chip, a sub-package and a first molding compound. The first chip is attached to the first substrate. The first molding compound encapsulates the first chip, the sub-package and the top surface of the first substrate. The bottom surface of the sub-package is attached to the first chip. The sub-package comprises a second substrate, a second chip and a second molding compound. The second substrate has a top surface and a bottom surface, and is electrically connected to the first chip. The second chip is attached to the top surface of the second substrate to which the second chip is electrically connected. The second molding compound encapsulates the second chip and part of the top surface of the second substrate. Whereby, the relative large area caused by the parallel arrangement of a plurality of conventional package structures can be reduced, and there is no need to redesign signal-transmitting path.

Abstract: The three-dimensional (3D) chip stacking technology developed in ASET is a leading technology for realization of a high-density and high-performance system-in-package (SIP). As for the advanced interconnection technology, a 20-/spl mu/m-pitch low impedance vertical interconnection through Cu through via (TV) within thin chips plays the following roles: wide signal bus and very short electrical path for high-frequency signal transmission, strong power supplies and stable ground lines. The vertical interconnection was fabricated by inter chip connection (ICC) process, which includes Cu bump bonding (CBB) utilizing Cu-Sn diffusion for connecting Cu TVs without the formation of bumps on the chip back surface and encapsulation micro thin gap between chips. We elucidate the Cu-Sn diffusion phenomena and Cu oxide influence which were important CBB issues to realize the minute interconnection of Cu TVs. The temperature cycling test (TCT) was performed on chip on chip (COC) and 3D chip stacking structures fabricated by ICC process, and over 1,000 cycles reliability was confirmed. The consistent fabrication of vertical interconnection was realized. Then, we conducted the two important electrical evaluations. One is the DC resistance of the vertical interconnection, which measured only 15.4 m/spl Omega/ per layer. Another was the signal transmission delay, and only 0.9 ps was confirmed. Therefore, the vertical interconnection with Cu TV and ICC demonstrates the excellent capability of high performance interconnections on 3D chip stacking package. In addition, the micro scale strip line was evaluated to realize advanced SIP. The eye diagram on 3 Gbps indicated sufficient transmission. We will be able to realize high performance advanced SIP utilizing the vertical interconnection and high-speed horizontal line.

Abstract: Apparatus and method are disclosed for digital authentication and verification. In one embodiment, authentication involves storing a cryptographic key and a look up table (LUT), generating an access code using the cryptographic key; generating multiple parallel BPSK symbols based upon the access code; converting the BPSK symbols into multiple tones encoded with the access code using the LUT; and outputting the multiple tones encoded with the access code for authentication. In another embodiment, verification involves receiving multiple tones encoded with an access code; generating multiple parallel BPSK symbols from the multiple tones; converting the BPSK symbols into an encoded interleaved bit stream of the access code; de-interleaving the encoded interleaved bit stream; and recovering the access code from the encoded de-interleaved bit stream.

Abstract: A multi-chip electronic package which utilizes an organic, laminate chip carrier and a pair of semiconductor chips positioned on an upper surface of the carrier in a stacked orientation The organic, laminate chip carrier is comprised of a plurality of conductive planes and dielectric layers and couples one or both of the chips to underlying conductors on the bottom surface thereof The carrier may include a high-speed portion to assure high-frequency connection between the semiconductor chips and may also include an internal capacitor and/or thermally conductive member for enhanced operational capabilities The first chip, eg, an ASIC chip, is solder bonded to the carrier while the second chip, eg, a memory chip, is secured to the first chip's upper surface and coupled to the carrier using a plurality of wirebond connections