Showing papers on "Chip published in 2001"
1 May 2001
TL;DR: This paper analyzes the limitations of the existing interconnect technologies and design methodologies and presents a novel three-dimensional chip design strategy that exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologies to realize a system-on-a-chip (SoC) design.
Abstract: Performance of deep-submicrometer very large scale integrated (VLSI) circuits is being increasingly dominated by the interconnects due to decreasing wire pitch and increasing die size. Additionally, heterogeneous integration of different technologies in one single chip is becoming increasingly desirable, for which planar (two-dimensional) ICs may not be suitable. This paper analyzes the limitations of the existing interconnect technologies and design methodologies and presents a novel three-dimensional (3-D) chip design strategy that exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologies to realize a system-on-a-chip (SoC) design. A comprehensive analytical treatment of these 3-D ICs has been presented and it has been shown that by simply dividing a planar chip into separate blocks, each occurring a separate physical level interconnected by short and vertical interlayer interconnects (VILICs), significant improvement in performance and reduction in wire-limited chip area can be achieved, without the aid of any other circuit or design innovations. A scheme to optimize the interconnect distribution among different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis for a two-layer 3-D chip. Furthermore, one of the major concerns in 3-D ICs arising due to power dissipation problems has been analyzed and an analytical model has been presented to estimate the temperatures of the different active layers. It is demonstrated that advancement in heat sinking technology will be necessary in order to extract maximum performance from these chips. Implications of 3-D device architecture on several design issues have also been discussed with special attention to SoC design strategies. Finally some of the promising technologies for manufacturing 3-D ICs have been outlined.
1,139 citations
TL;DR: In this paper, a 352/spl times/288 pixel CMOS image sensor chip with per-pixel single-slope ADC and dynamic memory in a standard digital 0.18-/spl mu/m CMOS process is described.
Abstract: A 352/spl times/288 pixel CMOS image sensor chip with per-pixel single-slope ADC and dynamic memory in a standard digital 0.18-/spl mu/m CMOS process is described. The chip performs "snapshot" image acquisition, parallel 8-bit A/D conversion, and digital readout at continuous rate of 10000 frames/s or 1 Gpixels/s with power consumption of 50 mW. Each pixel consists of a photogate circuit, a three-stage comparator, and an 8-bit 3T dynamic memory comprising a total of 37 transistors in 9.4/spl times/9.4 /spl mu/m with a fill factor of 15%. The photogate quantum efficiency is 13.6%, and the sensor conversion gain is 13.1 /spl mu/V/e/sup -/. At 1000 frames/s, measured integral nonlinearity is 0.22% over a 1-V range, rms temporal noise with digital CDS is 0.15%, and rms FPN with digital CDS is 0.027%. When operated at low frame rates, on-chip power management circuits permit complete powerdown between each frame conversion and readout. The digitized pixel data is read out over a 64-bit (8-pixel) wide bus operating at 167 MHz, i.e., over 1.33 GB/s. The chip is suitable for general high-speed imaging applications as well as for the implementation of several still and standard video rate applications that benefit from high-speed capture, such as dynamic range enhancement, motion estimation and compensation, and image stabilization.
421 citations
Patent•
30 Aug 2001
TL;DR: In this article, a low-pin-count chip package including a die pad for receiving a semiconductor chip and a plurality of connection pads electrically coupled to the semiconductor chips is described.
Abstract: A low-pin-count chip package including a die pad for receiving a semiconductor chip and a plurality of connection pads electrically coupled to the semiconductor chip. The semiconductor chip, the die pad, and the connection pads are encapsulated by a package body in a manner that the lower surfaces of the die pad and the connection pads are exposed through the package body. The present invention is characterized in that the die pad and the connection pads have a T-shaped profile thereby prolonging the time for moisture diffusion into the package as well as enhancing the “locking” of the die pad and the connection pads in the package body. The present invention further provides a method of producing the low-pin-count chip package described above.
225 citations
Patent•
24 Aug 2001
TL;DR: In this paper, a semiconductor light source for illuminating a physical space has been invented, and a TE cooler and air circulation may be provided to enhance heat dissipation, and an AC/DC converter may be included in the light source fitting.
Abstract: A semiconductor light source for illuminating a physical space has been invented. In various embodiments of the invention, a semiconductor such as and LED chip, laser chip, LED chip array, laser array, an array of chips, or a VCSEL chip is mounted on a heat sink. The heat sink may have multiple panels for mounting chips in various orientations. The chips may be mounted directly to a primary heat sink which is in turn mounted to a multi-panel secondary heat sink. A TE cooler and air circulation may be provided to enhance heat dissipation. An AC/DC converter may be included in the light source fitting.
216 citations
TL;DR: In this paper, a range of elementary optical coding and decoding experiments employing superstructured fiber Bragg grating (SSFBG) components are reported, showing that the SSFBG approach allows high-quality unipolar and bipolar coding.
Abstract: We report a range of elementary optical coding and decoding experiments employing superstructured fiber Bragg grating (SSFBG) components: first, we perform a comparative study of the relative merits of bipolar and unipolar coding: decoding schemes and show that the SSFBG approach allows high-quality unipolar and bipolar coding. A performance close to that-theoretically predicted for seven-chip, 160-Gchip/s M-sequence codes is obtained. Second, we report the fabrication and performance of 63-chip, 160-Gchip/s, bipolar Gold sequence grating pairs. These codes are at least eight times longer than those generated by any other scheme based on fiber grating technology so far reported. Last, we describe a range of transmission system experiments for both the seven- and 63-bit bipolar grating pairs. Error-free performance is obtained over transmission distances of /spl sim/25 km of standard fiber. In addition, we have demonstrated error-free performance under multiuser operation (two simultaneous users). Our results highlight the precision and flexibility of our particular grating writing process and show that SSFBG technology represents a promising technology not just for optical code division multiple access (OCDMA) but also for an extended range of other pulse-shaping optical processing applications.
211 citations
Patent•
31 Aug 2001
TL;DR: In this article, a light-emitting device is arranged on the surface of a circuit substrate whose surface is flat and at the same time, is molded by a lighttransmitting resin.
Abstract: PROBLEM TO BE SOLVED: To provide a light-emitting device for improving directivity and brightness. SOLUTION: In a light-emitting device 1, where an LED chip 4 is arranged on the surface of a circuit substrate 2 whose surface is flat and at the same time, is molded by a light-transmitting resin 6, a thick-film reflection covering 5 is formed in contact with the light-transmitting resin 6 on the surface of the substrate 2, so that the LED chip 4 is surrounded.
177 citations
TL;DR: The design of a prototype receiver chip dedicated to a distributed sensors network and based on a direct-conversion architecture, which achieves a -95 dBm sensitivity for a data rate of 24 kb/s and consumes only 1 mW in receive mode.
Abstract: A broad range of high-volume consumer applications require low-power battery-operated wireless microsystems and sensors These systems should conciliate a sufficient battery lifetime with reduced dimensions, low cost, and versatility Their design highlights the tradeoff between performance, lifetime, cost, and power consumption Also, special circuit and design techniques are needed to comply with the reduced supply voltage (down to 1 V, for single battery cell operation) These considerations are illustrated by the design of a prototype receiver chip realized in a standard 05-/spl mu/m digital CMOS process with 06-V threshold voltage The chip is dedicated to a distributed sensors network and is based on a direct-conversion architecture The circuit operates at 1-V power supply in the 434-MHz European ISM band and consumes only 1 mW in receive mode It achieves a -95 dBm sensitivity for a data rate of 24 kb/s
150 citations
Patent•
12 Oct 2001TL;DR: An integrated circuit chip package comprising a lead frame having an integrated circuit die electrically connected thereto is a package body as mentioned in this paper, which includes the central portion which is circumvented by a peripheral portion defining opposed top and bottom surfaces.
Abstract: An integrated circuit chip package comprising a lead frame having an integrated circuit die electrically connected thereto. Partially encapsulating the lead frame and the integrated circuit die is a package body. The package body includes the central portion which is circumvented by a peripheral portion defining opposed top and bottom surfaces. Disposed in at least one of the top and bottom surfaces of the peripheral portion of the package body is a singulation crease. The singulation crease, which is formed in the package body during its molding process, is used to provide a stress concentration line which reduces stress along the edge of the chip package and avoids chipping and cracking problems during the punch singulation process used to complete the manufacture of the same.
150 citations
Patent•
24 Oct 2001
TL;DR: A forward link design employing CDMA (code division multiple access) technologies in which time division multiplexing is employed between data and control information on the forward link to service multiple users per slot is provided in this paper.
Abstract: A forward link design is provided employing CDMA (code division multiple access) technologies in which time division multiplexing is employed between data and control information on the forward link to service multiple users per slot Another forward link design employing CDMA (code division multiple access) technologies is provided in which code division multiplexing between data and control information is employed on the forward link to service multiple users per slot, which is preferably backwards compatible with legacy standards such as IS2000A A reverse link design is also provided
147 citations
Patent•
19 Apr 2001TL;DR: In this paper, a plurality of semiconductor chips with the same structure are stacked to construct a multichip semiconductor device, and an optional circuit is formed, where fuses corresponding to the stacked-stage number of each chip are formed and selectively cut off so as to permit each chip to individually receive a chip control signal.
Abstract: A plurality of semiconductor chips with the same structure are stacked to construct a multichip semiconductor device. In each of the semiconductor chips, an optional circuit is formed. In the optional circuit, fuses corresponding to the stacked-stage number of each chip are formed and the fuses are selectively cut off so as to permit each chip to individually receive a chip control signal.
142 citations
TL;DR: A new generation of contactless smart card chip which integrates an on-chip coil connected to a power reception system and an emitter/receiver module compatible with the ISO 14443 standard, together with an asynchronous quasi-delay insensitive (QDI) 8-bit microcontroller.
Abstract: This paper describes a new generation of contactless smart card chip which integrates an on-chip coil connected to a power reception system and an emitter/receiver module compatible with the ISO 14443 standard, together with an asynchronous quasi-delay insensitive (QDI) 8-bit microcontroller. Beyond the contactless smart card application field, this new chip demonstrates that system-on-chip integrating power reception and management, radio-frequency communication, and signal processing is feasible. It associates analog/digital parts as well as synchronous/asynchronous logics and has been fabricated in a CMOS six metal layers 0.25-/spl mu/m technology from STMicroelectronics.
IBM1
TL;DR: The fourth-generation POWER processor as discussed by the authors contains 170M transistors and includes 2 microprocessor cores, shared L2, directory for an off-chip L3, and all logic needed to interconnect multiple chips to form an SMP.
Abstract: The fourth-generation POWER processor chip contains 170M transistors and includes 2 microprocessor cores, shared L2, directory for an off-chip L3, and all logic needed to interconnect multiple chips to form an SMP. It is implemented in a 0.18 /spl mu/m SOI technology, with 7 layers of Cu interconnect, and functions in systems at 1.1 GHz, and dissipates 115 W at 1.5 V.
Patent•
4 Dec 2001
TL;DR: In this paper, a chip for both bone conduction and air conduction sensing is presented, which can be used in a voice communication device with either an integrated circuit or an external component.
Abstract: The present invention is a chip for use in a voice communication device. The chip provides for both bone conduction sensing and air conduction sensing. The chip includes a bone conduction sensing pattern disposed within the chip and a microphone sensing pattern disposed within the chip. In addition, the chip can optionally include an integrated circuit portion interconnected to the bone conduction sensing pattern and the microphone sensing pattern. The pattern can be of a piezoelectric polymer, the patterns overlaying the substrate. Preferably, the bone conduction sensing pattern and the microphone sensing pattern are placed on opposite ends of the chip.
TL;DR: In this article, the EDX method is used to analyze the interaction between the cutting edge and the chip in the formation process, and the locus of cutter movement for the three types of chatter is illustrated to explain the relationship between the chip formation and the chatter behavior.
TL;DR: The possibility of all-digital (sourceto-eye) projection display was realized in 1987 with the invention of the Digital Micromirror Device™ projection display chip at Texas Instruments (TI) as discussed by the authors.
Abstract: The possibility of an all-digital (sourceto-eye) projection display was realized in 1987 with the invention of the Digital Micromirror Device™ projection display chip at Texas Instruments (TI). The DMD™ chip is a microelectromechanical systems (MEMS) array of fast digital micromirrors, monolithically integrated onto and controlled by an underlying silicon memory chip. Digital Light Processing™ projection displays are based on the DMD chip. DLP™ projection displays present bright, seamless images to the eye that have high image fidelity, and stability.
Patent•
IBM1
TL;DR: In this article, a Network Processor Complex (NP) is formed from a plurality of operatively coupled chips, which includes a network processor complex (NPC) Chip coupled to a Data Flow Chip and Data Store Memory coupled to the Data FlowChip.
Abstract: A Network Processor (NP) is formed from a plurality of operatively coupled chips. The NP includes a Network Processor Complex (NPC) Chip coupled to a Data Flow Chip and Data Store Memory coupled to the Data Flow Chip. An optional Scheduler Chip is coupled to the Data Flow Chip. The named components are replicated to create a symmetric ingress and egress structure. Communications between the chips are provided by a pair of Chip to Chip Macros, one of each operatively positioned on one of the chips, and a Chip to Chip Bus Interface operatively coupling the Chip to Chip Macros.
Patent•
7 Mar 2001
TL;DR: In this paper, a sensing device includes an RFID chip and a differential variable reluctance transducer (DVRT) sensor that can be read remotely with electromagnetic power provided to the device from a remote reader.
Abstract: A sensing device includes an RFID chip and a differential variable reluctance transducer (DVRT) sensor that can be read remotely with electromagnetic power provided to the device from a remote reader. The ac signal provided to the device by inductance is used for powering the RFID chip and exciting the sensor. Data read from the sensor can also be transmitted back to the reader using the power provided by the reader. The sensor circuit uses a lower amount of current than the RFID chip, so it does not contribute appreciably to device power requirements.
Patent•
22 Aug 2001
TL;DR: In this paper, a method and apparatus for reducing or eliminating the transmitter signal leakage, i.e., transmitter noise, in the receiver path of an RF communications system operating in full duplex mode is provided.
Abstract: A method and apparatus is provided for reducing or eliminating the transmitter signal leakage, i.e., transmitter noise, in the receiver path of an RF communications system operating in full duplex mode. In an embodiment of the present invention, a noise cancellation loop produces an estimated transmitter signal leakage and cancels it from the receiver path to produce a received signal with little or no transmitter noise. Some of the advantages are that there is significant improvement in the isolation between the transmitter/receiver circuits, the size of the RF communications circuitry may be reduced, and the RF transmit module along with the RF receive module may be incorporated into a single RF IC chip.
Patent•
25 Sep 2001TL;DR: In this article, a set of semiconductor integrated circuit (SIC) chips are stacked in a semiconductor device with a plurality of IC chips, each of which has a holding circuit holding identification information about the chip, electrically written in the chip.
Abstract: Disclosed is a stacked type semiconductor device having a plurality of semiconductor integrated circuit chips stacked, each of the semiconductor integrated circuit chips comprising a holding circuit holding identification information about the chip, electrically written in the chip, an identification information setting circuit setting the identification information about the chip, in the holding circuit after the plurality of semiconductor integrated circuit chips have been stacked, and at least one setting terminal used to set the identification information about the chip, in the holding circuit, wherein the at least one setting terminal of any semiconductor integrated circuit chip is connected to the at least one corresponding setting terminal of any other semiconductor integrated circuit chip.
TL;DR: In this paper, a bidirectional optical interconnect between two printed circuit boards containing optoelectronic (OE) very large scale integration (VLSI) circuits was constructed using vertical cavity surface emitting lasers (VCSELs) and photodiodes (PDs).
Abstract: Two-dimensional parallel optical interconnects (2-D-POIs) are capable of providing large connectivity between elements in computing and switching systems Using this technology we have demonstrated a bidirectional optical interconnect between two printed circuit boards containing optoelectronic (OE) very large scale integration (VLSI) circuits The OE-VLSI circuits were constructed using vertical cavity surface emitting lasers (VCSELs) and photodiodes (PDs) flip-chip bump-bonded to a 035-/spl mu/m complementary metal-oxide-semiconductor (CMOS) chip The CMOS was comprised of 256 laser driver circuits, 256 receiver circuits, and the corresponding buffering and control circuits required to operate the large transceiver array This is the first system, to our knowledge, to send bidirectional data optically between OE-VLSI chips that have both VCSELs and photodiodes cointegrated on the same substrate
TL;DR: In this paper, a coupled thermo-mechanical model of plane-strain orthogonal metal cutting with continuous chip formation is presented using the commercial implicit finite element code MARC.
Patent•
8 Jun 2001
TL;DR: In this article, the authors propose a semiconductor device manufacturing method that allows to eliminate a dicing tape and a push-up pin or the like, which are conventionally used, in a series of semiconductor devices manufacturing steps.
Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method that allows to eliminate a dicing tape and a push-up pin or the like, which are conventionally used, in a series of semiconductor device manufacturing steps. SOLUTION: A first manufacturing method for a semiconductor device is composed of a step for sticking a surface protection sheet on a circuit face of a semiconductor wafer having a surface formed with a circuit, a step for grinding a rear face of the wafer, a step for dividing the wafer into individual pieces by performing full-cut dicing of the wafer from the ground-face side for each circuit while the wafer is being supported by the surface protection sheet, a step for suckingly fixing the wafer to a suction table, which has a plurality of independently-controllable suction parts so as to suckingly fix the wafer as a whole, while arranging the ground face of the wafer oppositely to the suction table, a step for exfoliating and removing the surface protection sheet from the wafer divided into individual pieces, a step for partially releasing or weakening a suction force by controlling each suction part of the suction table so as to pick up the wafer divided into individual pieces for each chip, and a step for bonding each chip to a semiconductor substrate. COPYRIGHT: (C)2008,JPO&INPIT
Patent•
20 Sep 2001TL;DR: In this article, the chip file assembly is used for the mechanical and electrical coupling of a plurality of edge-mountable chips to a bus of a circuit board with relative ease, and the chip package is configured such that the chip mates with the base in retaining the chip in the base.
Abstract: A chip socket assembly provides for the mechanical and electrical coupling of edge-mountable chips to a bus of a circuit board with relative ease. An edge-mountable chip may be placed in a slot defined by a base. A clip may be attached to the base to retain the chip in the base. Alternatively, the base and the package of the chip may be configured such that the chip mates with the base in retaining the chip in the base. With the chip socket assembly, users may add, remove, or replace single chips and therefore expand the functionality of a system with the granularity of a single chip in a relatively easy manner. A chip file assembly may also be used to provide for the mechanical and electrical coupling of a plurality of edge-mountable chips to a bus of a circuit board with relative ease. Assemblies for securing horizontal chip packages are also described.
TL;DR: This work addresses several issues related to the design of optimal test access architectures that minimize testing time, including the assignment of cores to test buses, distribution of test data width between multiple test bus, and analysis oftest data width required to satisfy an upper bound on the testing time.
Abstract: Test access is a major problem for core-based system-on-a-chip (SOC) designs. Since embedded cores in an SOC are not directly accessible via chip inputs and outputs, special access mechanisms are required to test them at the system level. An efficient test access architecture should also reduce test cost by minimizing test application time. We address several issues related to the design of optimal test access architectures that minimize testing time., including the assignment of cores to test buses, distribution of test data width between multiple test buses, and analysis of test data width required to satisfy an upper bound on the testing time. Even though the decision versions of all these problems are shown to be NP-complete, they can be solved exactly for practical instances using integer linear programming (ILP). As a case study, the ILP models for two hypothetical but nontrivial systems are solved using a public-domain ILP software package.
Patent•
6 Apr 2001
TL;DR: In this paper, a diffusion layer region is provided at the surface part of a semiconductor substrate and a power supply pad 14 is connected via a substrate contact, thus supplying power supply voltage from the diffusion region to an internal circuit block.
Abstract: PROBLEM TO BE SOLVED: To reduce chip size by reducing the area of a wiring region in an IC chip having an internal circuit block. SOLUTION: For example, a diffusion layer region 12 is provided at the surface part of a semiconductor substrate 11, and the diffusion layer region 12 and a power supply pad 14 are connected via a substrate contact 16, thus supplying a power supply voltage from the power supply pad 14 to an internal circuit block 21, via only the semiconductor substrate 11 as shown by the arrow A.
Patent•
4 May 2001
TL;DR: In this article, a thermal enhanced ball grid array (TBE) is presented, which includes a metal core layer and at least a first patterned wiring layer provided thereon.
Abstract: A thermal enhanced ball grid array package is provided. The substrate for the package includes a metal core layer and at least a first patterned wiring layer provided thereon. A first insulating layer is provided between the first patterned wiring layer and the metal core layer. At least a second patterned wiring layer is provided on the substrate, opposite to the surface having the first patterned wiring layer. A second insulating layer having solder balls between the second patterned wiring layer and the metal core layer. The second patterned wiring layer is electrically connected to the first patterned wiring layer. Blind vias are provided in the second patterned wiring layer and the second insulating layer. A heat conductive material or solder material is filled into the blind vias to form thermal balls. The heat from the chip to the metal core layer is transferred directly through the thermal balls.
Patent•
29 Jun 2001
TL;DR: In this paper, the problem of suppressing the shaking of a center pad chip and stably fixing it when mounted on a wiring board by facing down is addressed. But the problem is not addressed in this paper.
Abstract: PROBLEM TO BE SOLVED: To suppress the shaking of a center pad chip and to stably fix the center pad chip when the center pad chip is mounted on a wiring board by facing down. SOLUTION: A semiconductor device has a semiconductor chip having outer electrodes arranged near a center line on a semiconductor substrate in a straight line, the wiring board which is confronted with the main face of the semiconductor chip and in which a metal wiring corresponding to the outer electrode is installed, and projection electrode connecting the outer electrodes of the semiconductor chip and the metal wiring. The projections fixing the semiconductor chip and the wiring board are installed in an outer peripheral area on the main face of the semiconductor chip.
Patent•
31 Oct 2001TL;DR: A semiconductor structure and a method for forming the semiconductor structures, including a semiconductor chip and a conductive layer disposed over a portion of the chip, is described in this paper.
Abstract: A semiconductor structure and a method for forming the semiconductor structure, including a semiconductor chip and a conductive layer disposed over a portion of the chip, the conductive layer having a portion that extends beyond an edge of the chip. The chip includes a device, which can be an integrated circuit or a micro-mechanical device. The structure can also include a front layer extending beyond the edge of the chip, the conductive layer being disposed on the front layer.
Patent•
20 Jul 2001TL;DR: In this paper, the authors present methods, apparatuses, and systems for eliminating auto-and cross-correlation in weak signal CDMA systems, such as GPS systems.
Abstract: The present invention discloses methods, apparatuses, and systems for eliminating auto- and cross-correlation in weak signal CDMA systems, such as GPS systems. The invention uses parallel data paths that allow standard correlation of signals in parallel with verification of the lock signal to determine whether the system has locked onto the proper signal within the scanned signal window. The invention can be made with multiple CPUs, a single CPU with dual input modes, on multiple IC chips, or as a single IC chip solution for small, low cost reception, downconversion, correlation, and verification systems.
Patent•
[...]
TL;DR: In this article, a reverse wire-bonding technique is used to allow the topmost bent portions of a first set of bonding wires connected to the bottommost chip to be positioned above the substrate rather than above the bottom most chip.
Abstract: A multi-chip module is proposed, which is designed to pack two or more semiconductor chips in a stacked manner over a chip carrier in a single package. The proposed multi-chip module is characterized by the use of a reverse wire-bonding technique to allow the topmost bent portions of a first set of bonding wires connected to the bottommost chip to be positioned above the substrate rather than above the bottommost chip. Then, an adhesive layer is formed to a thickness that allows it to entirely wrap the part of the bonding wires that is positioned above the active surface of the bottommost chip to prevent the bonding wires connected to the bottommost chip to come in contact with at least one overlaid chip. This allows the prevention of voids between the two stacked chips in the encapsulation body. Moreover, the proposed multi-chip module allows the stacked chips to be variably-sized according actual needs without the problem of the bonding wires being damaged during the mounting of the overlaid chip. The overlaid chip is electrically connected to the substrate by a second set of bonding wires, and an encapsulation body is provided to encapsulate the first semiconductor chip, the first set of bonding wires, the second semiconductor chip, and the second set of bonding wires.