Abstract: A novel CMOS device architecture called silicon on nothing (SON) is proposed, which allows extremely thin (in the order of a few nanometers) buried dielectrics and silicon films to be fabricated with high resolution and uniformity guaranteed by epitaxial process. The SON process' allows the buried dielectric (which may be an oxide but also an-air gap) to be fabricated locally in dedicated parts of the chip, which may present advantages in terms of cost and facility of system-on-chip integration. The SON stack itself is physically confined to the under-gate-plus-spacer area of a device, thus enabling extremely shallow and highly doped extensions, while leaving the HDD (highly doped drain) junctions comfortably deep. Therefore, SON embodies the ideal device architecture taking the best elements from both bulk and SOI and getting rid of their drawbacks. According to simulation results, SON enable ables excellent Ion/Ioff trade-off, suppressed self-heating, low S/D series resistance, close to ideal subthreshold slope, and high immunity to SCE and DIBL down to ultimate device dimensions of 30 to 50 nm.

Abstract: The present invention relates to a method for fabricating high performance chip interconnects and packages by providing methods for depositing a conductive material in cavities of a substrate in a more efficient and time saving manner. This is accomplished by selectively removing portions of a seed layer from a top surface of a substrate and then depositing a conductive material in the cavities of the substrate, where portions of the seed layer remains in the cavities. Another method includes forming an oxide layer on the top surface of the substrate such that the conductive material can be deposited in the cavities without the material being formed on the top surface of the substrate. The present invention also discloses methods for forming multi-level interconnects and the corresponding structures.

Abstract: A new analytical cutting force model is proposed for micro-end-milling operations. The model calculates the chip thickness by considering the trajectory of the tool tip while the tool rotates and moves ahead continuously. The proposed approach allows the calculation of the cutting forces to be done accurately in typical micro-end-milling operations with very aggressively selected feed per tooth to tool radius ( ft/r) ratio. The difference of the simulated cutting forces between the proposed and conventional models can be experienced when ft/r is larger than 0.1. The estimated cutting force profile of the proposed model had good agreement with the experimental data. © 2000 Elsevier Science Ltd. All rights reserved.

Abstract: A semiconductor package having heat sink at the outer surface is constructed on a lead frame. The package comprises a chip, a die pad, a plurality of leads, a plurality of bonding wires, and a molding compound. The die pad has a first surface and a second surface, and the chip has its active surface bonded to the first surface of the die pad. The area of the die pad is smaller than the area of the chip in order to expose the bonding pads on the active surface of the chip. The leads having an inner lead portions and an outer lead portions are disposed at the periphery of the die pad, and the inner lead portions are electrically connected to the bonding pads by a plurality of bonding wires. The molding compound encapsulates the chip, the die pad, the inner lead portions of the leads, and the bonding wires. The second surface of the die pad is exposed on the top surface of the package structure while the outer lead portion of the leads is exposed at the side edge of the package structure.

Abstract: Through-chip conductors for low inductance chip-to-chip integration and off-chip connections in a semiconductor package is disclosed A semiconductor device has active devices on the front surface, a first through-chip conductor having first electrical/physical characteristics passing from the front surface of the device to the back surface, a second through-chip conductor having second electrical/physical characteristics passing to the back surface, and an off-chip or chip-to-chip connector electrically connecting the active devices on the front surface to a different level of packaging

Abstract: We study the performance of optical code-division multiple access (CDMA) systems using various receivers structures. Two general classes of receivers based on required electronic bandwidth are studied. Optical orthogonal codes (OOCs) are utilized as signature sequences and the performance studied in this paper takes into account the effect of all major noise sources, i.e., quantum shot-noise, dark current noise, and Gaussian circuit noise. Furthermore, this paper introduces a generalized method of analyzing the performance of various optical CDMA receiver structures. Required mean number of photon count per chip time for reliable transmission of data bits for various receiver structures is investigated. Finally, the advantages and disadvantages of various receiver structures are discussed.

Abstract: The design, construction and performance of the H1 silicon vertex detector is described. It consists of two cylindrical layers of double-sided, double-metal silicon sensors read out by a custom designed analog pipeline chip. The analog signals are transmitted by optical fibres to a custom-designed ADC board and are reduced on PowerPC processors. Details of the design and construction are given and performance figures from the first data-taking periods are presented.

Abstract: An integrated optoelectronic device includes an electric circuit unit, such as a bare chip of integrated electronic devices, and an optical device unit for performing at least a portion of the input and output of signals to and from the electronic circuit unit via optical signals. The electronic circuit unit and the optical device unit are packaged in a common package with contoured upper, lower and side surfaces, and the optical device unit is provided on a side surface of the package.

Abstract: A new code structure for spectral amplitude coding optical code division multiple access (CDMA) is proposed and analysed. It is shown that such codes can effectively suppress the intensity noise and in turn increase the number of active users and improve the bit error rate performance.

Abstract: This paper presents a technology for high density and low parasitic capacitance electrical interconnects to arrays of Capacitive Micromachined Ultrasonic Transducers (CMUTs) on a silicon chip. Vertical wafer feedthroughs (vias) connect an array of sensors or actuators from the front side (transducer side) to the backside (packaging side) of the chip. A 20 to 1 high aspect ratio 20 /spl mu/m diameter via is achieved by using Deep Reactive Ion Etching (DRIE). Reduction of the parasitic capacitance of the polysilicon pads to the substrate can be achieved by using Metal Insulator Semiconductor (MIS) operating in the depletion region. This three-dimensional architecture allows for elegant packaging through simple flip-chip bonding of the chip's back side to a printed circuit board (PCB) or a signal processing chip.

Abstract: Test access is a major problem for system-on-a-chip (SOC) designs. Since embedded cores in an SOC are not directly accessible via chip I/Os, special access mechanisms are required to test them after system integration. An efficient test access architecture should reduce test cost and time-to-market by minimizing test application time. We address several issues related to the design of test access architectures. Even though these design problems are NP-complete, they can be solved exactly using integer linear programming (ILP). As a case study, the ILP models for two hypothetical but representative systems are solved using a public-domain ILP software package.

Abstract: The invention relates to a module component having chip components buried in a circuit board, and a method of manufacturing the same, and more specifically it relates to a module component capable of obtaining desired circuit characteristics and functions stably if the size of the component is reduced, being produced very efficiently, and suited to machine mounting, and a method of manufacturing the same. According to the invention, since a desired circuit is composed by disposing a specific number of chip components according to a specified rule, it is not necessary to heat the buried chip components at high temperature when forming a module, chip components are obtained in specified values, and the circuit characteristics, functions, and dimensional precision are stably obtained exactly as designed, and moreover since the chip components are disposed according to a specified rule, it is easy to automate insertion of chip components and increase its operation speed, even if the size of the chip components is reduced, and the circuit composition may be flexibly and easily changed only by changing the inserting position and type of chip components.

Abstract: Provided is a vertically integrated (“chip-over-chip”) semiconductor package and packaging method. The invention provides higher packaging density and performance, including increased functionality, decreased signal propagation delays, improved circuit switching speed, lower thermal resistance and higher thermal dissipation measurements, relative to previous package designs. According to the invention, a semiconductor package may be composed of a flip chip (or chips) overlying one or more other flip chips, all electrically bonded to flip chip bond pads on a cavity-less semiconductor substrate. The upper and lower flips chips may be assembled in a variety of different configurations and may be thermally or electrically connected to each other. In a preferred embodiment, the flip chips, particularly the lower flip chip(s), are thinned so that the overall package height is within conventional ranges for traditional single chip packages. Packages in accordance with the invention have increased access speeds between chips and reduced total chip package footprint.

Abstract: An LSI chip has first electrodes. A chip carrier has a board, second electrodes arranged on a first surface of the board, third electrodes arranged on a second surface of the board, and wires connecting second electrodes to third electrode each other. Bumps combine the first electrodes of the LSI chip with the second electrodes of the chip carrier each other. Resin fills a space between a main surface of the LSI chip and a first surface of the board, so as to fix the bumps to each other. Ball electrodes are combined with third electrodes of the chip carrier.

Abstract: To form a micromachine package, bond pads on a front surface of a controller chip are aligned with corresponding traces on a front surface of a micromachine chip. The bond pads are physically connected to the traces thus mounting the controller chip as a flip chip to the micromachine chip. A bead is formed around a periphery of the controller chip. The bead and the controller chip form an enclosure around a micromachine area in the front surface of the micromachine chip. This enclosure protects the micromachine area from the ambient environment.

Abstract: A method of encoding data in the visible portion of a transmitted video signal without degrading display of the received video signal, and for decoding the data in the received video signal. Each group of data bits to be transmitted, referred to a data symbol, is associated with one of a number of longer predetermined sequences of chips. Each chip sequence is divided into a multiplicity of lines of chips, and each line of chips together with its inverse are embedded, in pairwise fashion, in respective pairs of line scans of the video signal prior to its transmission. Received pairs of line scans are operated upon to detect the lines of chips they represent, and each of the number of chip sequences is correlated with the detected line of chips to derive a correlation magnitude. The chip sequence with the largest correlation magnitude is selected as the chip sequence whose data symbol was transmitted.

Abstract: Channels are formed that pass through an active surface of a semiconductor substrate to provide isolation between adjacent active surface regions defining individual die locations. Bond pads on the substrate are bumped with intermediate conductive elements, after which a material used to encapsulate the active surface is applied, filling the channels and covering exposed peripheral edges of the active surface integrated circuitry. The encapsulant is then planarized to expose the ends of the bumps. External conductive elements such as solder balls are then formed on the exposed bump ends. The semiconductor wafer is diced in alignment with the channels to singulate the semiconductor devices, the encapsulant in the channels keeping the edges of the integrated circuitry substantially hermetically sealed.

Abstract: This paper presents a generic low-power sensor interface chip compatible with smart microsystems and a wide range of capacitive transducers. The interface chip is highly programmable, can communicate with an external microcontroller using a nine-line sensor bus standard, contains a switched-capacitor readout circuit, supports sensor self-test, and includes a temperature sensor. The circuit can interface with up to six external sensors and contains three internal programmable reference capacitors in the range of 0.15–8 pF. The chip measures 3.2×3.2 mm in a standard 3-μm single-metal double-poly p-well process, dissipates less than 2.2 mW from a single 5 V supply, and can resolve input capacitance variations of less than 1 fF in 10 Hz bandwidth.

Abstract: A method of manufacturing a semiconductor chip assembly includes providing a semiconductor chip and a conductive metal, wherein the chip includes a conductive pad, the conductive metal includes a dimple, and the pad is aligned with the dimple, etching the conductive metal on a side opposite the dimple such that the dimple forms a through-hole in the conductive metal, and forming a connection joint in the through-hole that electrically connects the conductive metal and the pad. The method may include mechanically attaching the chip to the conductive metal using an adhesive before forming the through-hole, and forming an opening in the adhesive directly beneath the through-hole thereby exposing the pad after mechanically attaching the chip to the conductive metal and before forming the connection joint.

Abstract: In digital communications, orthogonal pulse shapes are often used to represent message symbols for transmission through a channel. In this paper, the design of such pulse shapes is formulated as a convex semidefinite programming problem, from which a globally optimal pulse shape can be efficiently found. The formulation is used to design filters that achieve (a) the minimal bandwidth for a given filter length; (b) the minimal filter length for a given bandwidth; (c) the maximal robustness to timing error for a given bandwidth and filter length. Bandwidth is measured either in spectral energy concentration terms or with respect to a spectral mask. The effectiveness of the method is demonstrated by the design of waveforms with substantially improved performance over the "chip" waveforms specified in standards for digital mobile telecommunications.

Abstract: A method of making a stacked chip package comprises the steps of: (a) placing a first chip onto a substrate in a manner that solder bumps on the first chip are aligned with corresponding flip-chip pads formed on a surface of the substrate; (b) reflowing the solder bumps; (c) attaching a second chip to the first chip through an adhesive layer; (d) curing the adhesive layer; (e) forming an underfill between the first chip and the substrate; (f) curing the underfill; (g) electrically coupling the second chip to corresponding wire-bondable pads formed on the surface of the substrate; and (h) encapsulating the first chip and the second chip against a portion of the surface of the substrate. This invention is characterized in that the adhesive layer is cured before underfilling thereby forming a protection layer on the first chip. Therefore, the cured adhesive layer can help the first chip to resist stresses created during curing process of the underfill, thereby reducing the problem of die cracking.

Abstract: Semiconductor chip assemblies incorporating flexible, sheet-like elements having terminals thereon overlying the front or rear face of the chip to provide a compact unit. The terminals on the sheet-like element are movable with respect to the chip, so as to compensate for thermal expansion. A resilient element such as a compliant layer interposed between the chip and terminals permits independent movement of the individual terminals toward the chip driving engagement with a test probe assembly so as to permit reliable engagement despite tolerances.

Abstract: A spread spectrum receiver uses a comparison of the magnitude of the code correlation amplitudes at equal power at a one chip spacing to the magnitude at a central position there between to determine if multipath interference is present. The lead or lag error from constructive or destructive multipath interference may also be determined. Inaccuracies due to such interference may then be corrected or minimized by, for example, determining the residual code phase error and/or the prompt or accurate code phase delay.

Abstract: Custom design, in which the designer controls the physical structure of the chip, can greatly improve the speed, power, and delay of an ASIC chip without affecting design time. Through floorplanning and tiling data paths, the designer places the critical wires first, before the logic is placed. Crafted datapath cells structure wiring at the other end of the spectrum by keeping local wires short enabling the use of minimum sized drivers. Routing the wires first gives early visibility of timing issues, allows the design to be optimized to drive the exact wire load, and enables the use of fast circuit styles.

Abstract: On-chip inductance modeling of VLSI interconnects is presented which captures 3D geometry from layout design and process technology information. Analytical formulae are derived for quick and accurate inductance estimation which can be used in circuit simulations and whole chip extraction screening process. Circuit simulations show critical global wire inductive effects as well as power and ground inductive noise.

Abstract: Direct-sequence code-division multiple-access is considered for underwater acoustic communication networks. Unlike in the majority of spread-spectrum radio systems, intersymbol interference cannot be neglected, and time variability of the channel requires that receiver adaptation be performed at the chip, rather than the bit rate. Adaptive decision-feedback equalization, which has successfully been used for single-user underwater communications, is not directly applicable to spread-spectrum signals because of the delay in the despreading process and the lack of reliable chip decisions. To overcome this problem, a receiver is proposed which feeds back hypothesized, rather than the actual decisions. Numerical examples demonstrate the receiver's ability to cope with time varying channel distortions and preserve the processing gain when conventional, symbol-rate adaptive methods fail.

Abstract: This paper presents a low-power bit-serial Viterbi decoder chip with the code rate r=1/3 and the constraint length K=9 (256 states) for next generation wireless communication applications. The architecture of the add-compare-select (ACS) module is based on the bit-serial arithmetic and implemented with the pass transistor logic circuit. A cluster-based ACS placement and state metric routing topology is described for the 256 bit-serial ACS units, which achieves very high area efficiency. In the trace-back operation, a power efficient trace-back scheme, allowing higher memory read access rate than memory write in a time-multiplexing method, is implemented to reduce the number of iterations required to generate a decoded output. In addition, a low-power application-specific memory suitable for the function of survivor path memory has also been developed. The chip's core, implemented using 0.5-/spl mu/m CMOS technology, contains approximately 200 K transistors and occupies 2.46 mm by 4.17 mm area. This chip can achieve the decode rate of 20 Mb/s under 3.3 V and 2 Mb/s under 1.8 V. The measured power dissipation at 2 Mb/s under 1.8 V is only about 9.8 mW. The Viterbi decoder presented here can be applied to next generation wide-band code division multiple access (W-CDMA) systems.

Abstract: A system-on-chip interconnection structure and method uses unidirectional buses only, central shared memory controllers, separate interconnects for high-speed and low-speed peripherals, zero wait-state register accesses, application-specific memory map and peripherals, application-specific test methodology, allowances for cache controllers, and good fits with standard ASIC flow and tools.

Abstract: A system includes cascaded content addressable memory (CAM) chips connected to a common bus. Each CAM chip includes a CAM array, a self-timed signal generator and hit propagation and match address transfer circuits. Each CAM array including an array of core cells provides, through its encoder, hit and match address signals resulting from a search operation in response to a clock signal. Each match address transfer circuit transfers the match address signal to the common bus, in response to a self-timed signal, the hit signal and a propagation-in hit signal provided from an upstream CAM chip, so that more than one CAM chip is prevented from providing the match address signal to the common bus simultaneously. Each hit propagation circuit provides a propagation-out hit signal to a downstream CAM chip, in response to the self-timed signal, the hit signal and the propagation-in hit signal from the upstream CAM chip, so that a hit signal is propagated from an upstream CAM chip to a downstream CAM chip. Each CAM chip may include an extra row for providing a modelmiss signal or a modelhit signal which is used for a generating self-timed signal. Each word may be divided into two halves and two match lines of the two halves are coupled by a logic circuit. The system may also observe a multiple match status and the highest priority chip indicating a match.