TL;DR: This demonstration could represent the beginning of an era of chip-scale electronic–photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.
Abstract: An electronic–photonic microprocessor chip manufactured using a conventional microelectronics foundry process is demonstrated; the chip contains 70 million transistors and 850 photonic components and directly uses light to communicate to other chips. The rapid transfer of data between chips in computer systems and data centres has become one of the bottlenecks in modern information processing. One way of increasing speeds is to use optical connections rather than electrical wires and the past decade has seen significant efforts to develop silicon-based nanophotonic approaches to integrate such links within silicon chips, but incompatibility between the manufacturing processes used in electronics and photonics has proved a hindrance. Now Chen Sun et al. describe a 'system on a chip' microprocessor that successfully integrates electronics and photonics yet is produced using standard microelectronic chip fabrication techniques. The resulting microprocessor combines 70 million transistors and 850 photonic components and can communicate optically with the outside world. This result promises a way forward for new fast, low-power computing systems architectures. Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems—from mobile phones to large-scale data centres. These limitations can be overcome1,2,3 by using optical communications based on chip-scale electronic–photonic systems4,5,6,7 enabled by silicon-based nanophotonic devices8. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic–photonic chips9,10,11 are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic–photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a ‘zero-change’ approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics12, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors13,14,15,16. This demonstration could represent the beginning of an era of chip-scale electronic–photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.
TL;DR: An analysis of the chip geometry and the force system found in the case of orthogonal cutting accompanied by a type 2 chip has yielded a collection of useful equations which make possible the study of actual machining operations in terms of basic mechanical quantities as mentioned in this paper.
Abstract: An analysis of the chip geometry and the force system found in the case of orthogonal cutting accompanied by a type 2 chip has yielded a collection of useful equations which make possible the study of actual machining operations in terms of basic mechanical quantities. The shearing strain undergone by the metal during chip formation, and the velocities of shear and of chip flow are among the geometrical quantities which can be quantitatively determined. The force relationships permit calculation of such quantities as the various significant force components, stresses, the coefficient of friction between chip and cutting tool, and the work done in shearing the metal and in overcoming friction on the tool face. The experimental methods by which such analyses can be readily made are described. Observed and calculated values from typical tests are presented.
TL;DR: It is shown that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.
Abstract: With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.
TL;DR: In this article, a multiple access, spread spectrum communication system and method for providing high capacity communications to, from, or between a plurality of system users, using code-division-spread-spectrum communication signals is presented.
Abstract: A multiple access, spread spectrum communication system and method for providing high capacity communications to, from, or between a plurality of system users, using code-division-spread-spectrum communication signals. The communication system uses means for providing marginal isolation between user communication signals. The marginal isolation is provided by generating simultaneous multiple steerable beams; using an omni-directional antenna with polarization enhancement; using power control devices to adjust the output power for user generated communication signals either in response to their input activity level, or in accordance with a minimum allowable power for maintaining a communication link. The communication system can also employ a means for transmitting a predetermined pilot chip sequence contiguous with the code-division-spread-spectrum communication signals. In further embodiments the communication system employs a plurality of user terminals linked to each other or to other services through one or more terrestrial or satellite repeaters. Multiple satellite repeaters are operable in a new communication mode to obtain further gains in signal isolation.
TL;DR: This paper analyzes the limitations of the existing interconnect technologies and design methodologies and presents a novel three-dimensional chip design strategy that exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologies to realize a system-on-a-chip (SoC) design.
Abstract: Performance of deep-submicrometer very large scale integrated (VLSI) circuits is being increasingly dominated by the interconnects due to decreasing wire pitch and increasing die size. Additionally, heterogeneous integration of different technologies in one single chip is becoming increasingly desirable, for which planar (two-dimensional) ICs may not be suitable. This paper analyzes the limitations of the existing interconnect technologies and design methodologies and presents a novel three-dimensional (3-D) chip design strategy that exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologies to realize a system-on-a-chip (SoC) design. A comprehensive analytical treatment of these 3-D ICs has been presented and it has been shown that by simply dividing a planar chip into separate blocks, each occurring a separate physical level interconnected by short and vertical interlayer interconnects (VILICs), significant improvement in performance and reduction in wire-limited chip area can be achieved, without the aid of any other circuit or design innovations. A scheme to optimize the interconnect distribution among different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis for a two-layer 3-D chip. Furthermore, one of the major concerns in 3-D ICs arising due to power dissipation problems has been analyzed and an analytical model has been presented to estimate the temperatures of the different active layers. It is demonstrated that advancement in heat sinking technology will be necessary in order to extract maximum performance from these chips. Implications of 3-D device architecture on several design issues have also been discussed with special attention to SoC design strategies. Finally some of the promising technologies for manufacturing 3-D ICs have been outlined.