Charged-device model

Abstract: A novel diode-triggered silicon-controlled rectifier (DTSCR) (Mergens et al., 2003) electrostatic discharge (ESD) protection element is introduced for low-voltage application (signal and supply voltages /spl les/ 1.8 V) with extremely narrow ESD design margins. Trigger-voltage engineering in conjunction with fast and efficient SCR voltage clamping is applied for the protection of ultrasensitive circuit nodes, such as SiGe heterojunction bipolar transistor (HBT) base regions (e.g., f/sub Tmax/=45 GHz in BiCMOS 0.35-/spl mu/m LNA input) and thin gate oxides (e.g., t/sub ox/=1.7 nm in CMOS 0.09-/spl mu/m high-speed input). Ultrathin gate protection requires a reinforced trigger diode chain to avoid SCR trigger-speed issues resulting in critical trigger-voltage overshoots for very fast ESD transients such as a charged device model (CDM). SCR integration can be realized based on parasitic n-p-n/p-n-p inherent to CMOS devices or can alternatively be implemented based on vertical high-speed SiGe HBT with adjacent p+ SCR anode.

Abstract: A novel electrostatic discharge (ESD) protection circuit, which combines complementary low-voltage-triggered lateral SCR (LVTSCR) devices and the gate-coupling technique, is proposed to effectively protect the thinner gate oxide of deep submicron CMOS ICs without adding an extra ESD-implant mask. Gate-coupling technique is used to couple the ESD-transient voltage to the gates of the PMOS-triggered/NMOS-triggered lateral silicon controlled rectifier (SCR) (PTLSCR/NTLSCR) devices to turn on the lateral SCR devices during an ESD stress. The trigger voltage of gate-coupled lateral SCR devices can be significantly reduced by the coupling capacitor. Thus, the thinner gate oxide of the input buffers in deep-submicron low-voltage CMOS ICs can be fully protected against ESD damage. Experimental results have verified that this proposed ESD protection circuit with a trigger voltage about 7 V can provide 4.8 (3.3) times human-body-model (HBM) [machine-model (MM)] ESD failure levels while occupying 47% of layout area, as compared with a conventional CMOS ESD protection circuit.

Abstract: An ESD protection circuit for the pads of an integrated circuit (IC) using silicide-clad diffusions is disclosed. The circuit uses a robust N+ diode with N-well block, an output NFET and a large transient clamp, each with a distributed, integrated N-well drain resistor to prevent the IC from avalanching and leakage during the Human Body Model and Charged Device Model tests for ESD.

Abstract: An apparatus for protecting an integrated circuit against damage from electrostatic discharge (ESD) includes an ESD bus that is connected to multiple input pads through a respective diode. The ESD bus--the node to be protected--is coupled to the negative power supply bus (Vss) by a FET-triggered SCR circuit. In particular, the SCR circuit includes, equivalently, a PNP bipolar transistor, and an NPN bipolar transistor interconnected so that each transistor receives base current from the collector terminal of the other. A field effect transistor (FET) is configured to trigger the SCR into conduction, to thereby provide a low-impedance path to safely shunt ESD charge. The drain terminal of the FET is connected to an intermediate node of a resistance between the ESD bus, and the PNP emitter terminal. ESD charge on an input pad of the integrated circuit forward biases the respective diodes, and charges the ESD bus. When the voltage on the ESD bus reaches a predetermined threshold voltage, the FET drain region breaks down, and triggers the SCR circuit into conduction to shunt the charge on the ESD bus to Vss. The voltage drop occasioned by current flowing from the ESD bus to the intermediate node at the onset of the FET drain breakdown hastens the turn-on of the SCR, thus improving the response time for handling fast ESD events, such as those in accordance with the Charged Device Model (CDM).