Abstract: Exemplary embodiments of methods and apparatuses to dynamically redistribute computational processes in a system that includes a plurality of processing units are described. The power consumption, the performance, and the power/performance value are determined for various computational processes between a plurality of subsystems where each of the subsystems is capable of performing the computational processes. The computational processes are exemplarily graphics rendering process, image processing process, signal processing process, Bayer decoding process, or video decoding process, which can be performed by a central processing unit, a graphics processing units or a digital signal processing unit. In one embodiment, the distribution of computational processes between capable subsystems is based on a power setting, a performance setting, a dynamic setting or a value setting.

Abstract: This method is an error correction method such that, when an error is detected in a CPU with pipeline structure, a content of a register file is restored by a delayed register file which holds an execute completion state of an [Instruction N] correctly executed before this error, and a rollback control that re-executes an instruction from the [Instruction N+1] which is the next instruction of the [Instruction N] is performed. The method collects a parity check result of arbitrary Flip-Flops existing inside the CPU, and detects an error. As a result, the content of the register file is restored into the instruction execute completion state preceding to the instruction range likely to malfunction by the error, and the instruction can be roll backed from the beginning of the instruction range likely having malfunctioned by the error.

Abstract: A computer processor includes a decoder for decoding machine instructions and an execution unit for executing those instructions. The decoder and the execution unit are capable of decoding and executing vector instructions that include one or more format conversion indicators. For instance, the processor may be capable of executing a vector-load-convert-and-write (VLoadConWr) instruction that provides for loading data from memory to a vector register. The VLoadConWr instruction may include a format conversion indicator to indicate that the data from memory should be converted from a first format to a second format before the data is loaded into the vector register. Other embodiments are described and claimed.

Abstract: A system and method for digital management and control of power conversion from battery cells. The system utilizes a power management and conversion module that uses a CPU to maintain a high power conversion efficiency over a wide range of loads and to manage charge and discharge operation of the battery cells. The power management and conversion module includes the CPU, a current sense unit, a charge/discharge unit, a DC-to-DC conversion unit, a battery protection unit, a fuel gauge and an internal DC regulation unit. Through intelligent power conversion and charge/discharge operations, a given battery type is given the ability to emulate other battery types by conversion of the output voltage of the battery and adaptation of the charging scheme to suit the battery.

Abstract: A computer. A processor pipeline alternately executes instructions coded for first and second different computer architectures or coded to implement first and second different processing conventions. A memory stores instructions for execution by the processor pipeline, the memory being divided into pages for management by a virtual memory manager, a single address space of the memory having first and second pages. A memory unit fetches instructions from the memory for execution by the pipeline, and fetches stored indicator elements associated with respective memory pages of the single address space from which the instructions are to be fetched. Each indicator element is designed to store an indication of which of two different computer architectures and/or execution conventions under which instruction data of the associated page are to be executed by the processor pipeline. The memory unit and/or processor pipeline recognizes an execution flow from the first page, whose associated indicator element indicates the first architecture. or execution convention, to the second page, whose associated indicator element indicates the first architecture or execution convention. In response to the recognizing, a processing mode of the processor pipeline or a storage content of the memory adapts to effect execution of instructions in the architecture and/or under the convention indicated by the indicator element corresponding to the instruction's page.

Abstract: A system has at least one bus, a central processing unit (CPU) coupled with the bus, a memory coupled with the bus, a direct memory access (DMA) controller having a plurality of DMA channels and operating independently from the CPU and being coupled with the bus, wherein for access to the bus the DMA controller is programmable in a first mode to have priority over the CPU and in a second mode in which at least one DMA channel of the DMA controller is suspended from accessing the bus.

Abstract: An apparatus for encoding videos having a central processing unit and a memory, coupled to the central processing unit, is provided. The memory has an Internet protocol (IP) address pool having IP addresses and a video encoding module. The video encoding module has instructions for obtaining a video source having a plurality of sequential frames. The video encoding module further has instructions for assigning select frames in the plurality of sequential frames with at least one IP address from the IP address pool, thereby forming an encoded video containing at least one embedded IP address. The video encoding module further has instructions for removing the at least one IP address from the IP address pool that is in the encoded video and instructions for storing the encoded video.

Abstract: A computer system which includes a CPU for performing various processes by program control and storage elements which store at least one operating system and a BIOS, wherein upon starting a system, the CPU recognizes the system's own hardware configuration, and starts a selected one operating system stored in the storage elements in accordance with the recognized hardware configuration under the control of the BIOS.

Abstract: A judgment is made quickly about whether or not it is a memory or a chipset that is causing a performance bottleneck in an application program. A computer system of this invention includes at least one CPU, a controller that connects the CPU to a memory and to an I/O interface, in which the controller includes a response time measuring unit, which receives a request to access the memory and measures a response time taken to respond to the memory access request, a frequency counting unit, which measures an issue count of the memory access request, a measurement result storing unit, which stores a measurement result associating the response time with the corresponding issue count, and a measurement result control unit which outputs the measurement result stored in the measurement result storing unit when receiving a measurement result read request.

Abstract: A hardware-facilitated secure software execution environment provides protection of both program instructions and data against unauthorized access and/or execution to maintain confidentiality and integrity of the software or the data during distribution, in external memories, and during execution. The secure computing environment is achieved by using a hardware-based security method and apparatus to provide protection against software privacy and tampering. A Harvard architecture CPU core is instantiated on the same silicon chip along with encryption management unit (EMU) circuitry and secure key management unit (SKU) circuitry. Credential information acquired from one or more sources is combined by the SKU circuitry to generate one or more security keys provided to the EMU for use in decrypting encrypted program instructions and/or data that is obtained from a non-secure, off-chip source such as an external RAM, an information storage device or other network source. In a non-limiting illustrative example implementation, the EMU decrypts a single memory page of encrypted instructions or data per a corresponding encryption key provided by the SKU. Although instantiated on the same chip, the CPU core does not have direct access to the SKU circuitry or to encryption key information generated by the SKU.

Abstract: Modern graphics cards for computers, and especially their graphics processing units (GPUs), are designed for fast rendering of graphics In order to achieve this GPUs are equipped with a parallel architecture which can be exploited for general-purpose computing on GPU (GPGPU) as a complement to the central processing unit (CPU) In this paper GPGPU techniques are used to make a parallel GPU implementation of state-of-the-art recursive Bayesian estimation using particle filters (PF) The modifications made to obtain a parallel particle filter, especially for the resampling step, are discussed and the performance of the resulting GPU implementation is compared to one achieved with a traditional CPU implementation The resulting GPU filter is faster with the same accuracy as the CPU filter for many particles, and it shows how the particle filter can be parallelized

Abstract: A biomass harvesting system for harvesting agricultural plant growth from agricultural fields comprises a power source for providing mechanical and electric power to the system, a biomass accumulator for producing discrete units of accumulated biomass, a windrower for feeding biomass to the accumulator, a biomass quality analyzer for sensing and transmitting a set of quality characteristics of the biomass, a soil chemical analyzer for sensing and transmitting in real time soil chemical characteristics of the agricultural field soil, an active tracking system for identifying individual ones of the discrete units of accumulated biomass, and a central processing unit including a memory module storing an executable instruction set therein. The central processing unit executes the instruction set and integrates the sensed biomass quality characteristics and the sensed optimal quantity of biomass residue to remain on the field to determine a biomass quality index of the discrete units of accumulated biomass.

Abstract: The PAWiS (power aware wireless sensors) simulation framework facilitates design and simulation of wireless sensor network models. Main focus is given to power efficiency and therefore on capturing inefficiencies in various aspect of the system. These aspects include all layers of the communication system, the targeted class of application itself, the power supply and energy management, the central processing unit (CPU) and the sensor-actuator interface. The proposed simulation framework is based on the OMNeT++ discrete event simulator and provides PAWiS specific features (e.g. a mechanism to handle RF channel transmissions) to simulate, analyze and optimize the aforementioned aspects.

Abstract: The utility model provides a mobile telephone with speech input and speech dialing functions, comprising a microphone; a speech receiving circuit connected to the microphone; a central processing unit, designed to invoke a speech recognition program to recognize and process digital speech signals; a transceiver circuit, designed to modulate the digital speech signals from the central processing unit into radio-frequency signals; a mobile telephone antenna connected to the transceiver circuit; a speech recognition program storage unit connected to the central processing unit; and, a video output circuit and a display module that are connected to the central processing unit in sequence. The utility model has the following advantages: it is simple in design and easy to use, and can implement calling and control of mobile telephone functions, without the need for key input; with the speech dialing function and speech instruction function, the hands and eyes of the user can be liberated.

Abstract: A multi-graphics processor system includes a CPU; a first GPU connected to the CPU via an input/output interface; and a second GPU connected to the first GPU via a second-GPU interface. The first GPU is provided with a second-GPU bus for communicating the CPU and the second GPU via the second-GPU interface. The CPU communicates with the second GPU via the second-GPU bus after receiving a signal indicating the timing of the data communication.

Abstract: Systems, methods and program products for a first central processing unit (CPU) configured to perform tasks that do not require manipulation of sensitive information and a second CPU that is configured to perform tasks that manipulate the sensitive information on behalf of the first CPU. The first CPU and the second CPU can communicate through a secure interface. The first CPU cannot access the sensitive information within the second CPU.

Abstract: There has recently been much interest in stream processing, both in industry (e.g., Cell, NVIDIA G80, ATI R580) and academia (e.g., Stanford Merrimac, MIT RAW), with stream programs becoming increasingly popular for both media and more general-purpose computing. Although a special style of programming called stream programming is needed to target these stream architectures, huge performance benefits can be achieved. In this paper, we minimally add architectural features to commodity general-purpose processors (e.g., Intel/AMD) to efficiently support the stream execution model. We design the extensions to reuse existing components of the general-purpose processor hardware as much as possible by investigating low-cost modifications to the CPU caches, hardware prefetcher, and the execution core. With a less than 1% increase in die area along with judicious use of a software runtime system, we can efficiently support stream programming on traditional processor cores. We evaluate our techniques by running scientific applications on a cycle-level simulation system. The results show that our system executes stream programs as efficiently as possible, limited only by the ALU performance and the memory bandwidth needed to feed the ALUs.

Abstract: A kernel-aware debugging system, medium, and method. The kernel-aware debugging system may include a kernel-aware debugging interface including a conditional breakpoint setting unit which sets a kernel-aware conditional breakpoint by checking a currently operating object inside a kernel of a target system when a central processing unit (CPU) of the target system stops operating at a particular position where the breakpoint is set and making the CPU proceed to operate when it is determined that it is not intended that the currently operating object be debugged. Moreover, the kernel-aware debugging interface may include a unit which stores control flow information for detecting faults due to asynchronous events, a profiling unit which collects profile information and allows back-tracing when faults occur, and a unit which debugs a synchronization problem between multitasks.

Abstract: A method and system for migrating a computer environment, such as a virtual machine, from a first blade server to a second blade server includes storing data generated by the first and second blade servers on a shared hard drive and transferring a logic unit number from the first blade server to the second blade server. The logic unit number identifies a location of the shared hard drive used by the first blade server to store data. Additionally, the state of the central processing unit of the first blade server may be transferred to the second blade server.

Abstract: A wearable computer for use in a process control environment includes a central processing unit, a memory and a number of other or integral devices such as a display, a microphone, a video camera, a voice recognition unit and a remote communication device that communicates with a host computer. The wearable computer provide information pertaining to one or more devices within a process control system (such as diagnostic information, help information, operator overviews, schematics or process parameter information) via the display. The wearable computer also executes a voice recognition routine that processes a received voice signal to automatically identify user inputs such as commands, process control devices within the field of view of the wearer, device tags, etc. and uses the user inputs to change a display, to alter a process signal, to retrieve device information etc.

Abstract: Non-rigid multi-modal registration of images/volumes is becoming increasingly necessary in many medical settings. While efficient registration algorithms have been published, the speed of the solutions is a problem in clinical applications. Harnessing the computational power of graphics processing unit (GPU) for general purpose computations has become increasingly popular in order to speed up algorithms further, but the algorithms have to be adapted to the data-parallel, streaming model of the GPU. This paper describes the implementation of a non-rigid, multi-modal registration using mutual information and the Kullback-Leibler divergence between observed and learned joint intensity distributions. The entire registration process is implemented on the GPU, including a GPU-friendly computation of two-dimensional histograms using vertex texture fetches as well as an implementation of recursive Gaussian filtering on the GPU. Since the computation is performed on the GPU, interactive visualization of the registration process can be done without bus transfer between main memory and video memory. This allows the user to observe the registration process and to evaluate the result more easily. Two hybrid approaches distributing the computation between the GPU and CPU are discussed. The first approach uses the CPU for lower resolutions and the GPU for higher resolutions, the second approach uses the GPU to compute a first approximation to the registration that is used as starting point for registration on the CPU using double-precision. The results of the CPU implementation are compared to the different approaches using the GPU regarding speed as well as image quality. The GPU performs up to 5 times faster per iteration than the CPU implementation.

Abstract: This paper presents a simulator that uses graphical animation to convey the concepts of various scheduling algorithms for a single CPU. The simulator is unique in a number of respects. First, it uses a more realistic process model that can be configured easily by the user. Second, it graphically depicts each process in terms of what the process is currently doing against time. Using this representation, it becomes much easier to understand what is going on inside the system and why a different set of processes is a candidate for the allocation of the CPU at different time. A third unique feature of the simulator is that it allows the user to test and increase his understanding of the concepts studied by making his own scheduling decisions, through the very easy-to-use graphical user interface of the simulator. The simulator can be used by students in operating system courses or by anyone interested in learning CPU scheduling algorithms in an easier and a more effective way.

Abstract: The method for navigation instrument to search interested points along the navigation path includes: for the CPU unit in the navigation instrument to receive the attribute information the user inputs by means of the touch screen during navigation; for the CPU unit to detect the current position based on the GPS signal the GPS receiver accepts and read out all the interested points from the map database; for the CPU unit to check out the interested points of the attribute and to show these interested points in the touch screen.

Abstract: There is provided a system and method for toggling between system power modes based on motion detection. More specifically, in one embodiment, there is provided a video unit (100), comprising a central processing unit (106), a low-power processor (108) coupled to the central processing unit (106), and a motion detector (118) coupled to the low-power processor (108), wherein the low-power processor (108) is configured to initiate the central processing unit (106) into a ready power mode as a result of motion detected by the motion detector (118).

Abstract: A software development system according to the present invention comprises a business component storage layer for storing at least one business standard component of a program; a business component setting layer for setting attribute information of each business standard object, including object type, operating method, execution condition, execution sequence and database (DB) connection information; an application program execution layer for operating and controlling the object in the business component storage layer by the attribute information of the objects set by the user, and performing comparison, execution or calculation according to logic defined in script language; and an environment abstraction layer for controlling information technology (IT) infrastructure including an operating system of a computer, a central processing unit (CPU), a memory, a database management system (DBMS), network and display apparatus.

Abstract: A pipelined out-of-order process and system for handling data packets in a network device. The process and system are scalable to support throughput in excess of 10 Gbps. The system includes a set of processing cores that offload the table look up operations and similar operations from the central processing unit. The central processing unit receives the requisite data needed for performing forwarding, routing, NAT, firewall maintenance and similar operation on data packets from the set of processing cores.

Abstract: This invention discloses one electron device, which comprises central processor, memory, switch unit, basic input and output system, wherein, the memory sets two BIOS program memory areas; the BIOS switch unit is to electrify the device and to trigger the electron device switch from one BIOS program memory area to other electron device; the switch unit is to electrify the device or to break the CPU to the division address wire and to conduct division wire for electron device start. This invention also discloses one start method and BIOS update method.