Abstract: Apparatus, method and computer program product are provided for digitally processing an encrypted data stream scrambled, for example, according to content scrambling system (CSS) technology. This digital processing insures against communication of clear data within the computer system from a central processing unit (CPU) to any accessible structure, such as memory or a system bus. Descrambling of the (CSS) scrambled data stream occurs within a module executing on the CPU, which is followed by re-encryption of the data prior to transfer from the CPU. By so processing the data, integrity of copyrighted material is maintained, while allowing for software descrambling of the CSS encrypted data stream. Various techniques for establishing the encryption/decryption algorithm pair employed are described. Decryption of the re-encrypted data can occur at a receiving software module and/or a receiving hardware device, such as a decoder.

Abstract: A parallel processing architecture for a digital processor capable of alternately operating in a single threaded mode, a SIMD (single instruction, multiple data) mode and a MIMD (multiple instructions, multiple data) mode. The instruction set for the processor includes instructions for switching between modes and exchanging data between the parallel processing paths. The hardware in any instruction path or portion of an instruction path which is not being used is deactivated to save power.

Abstract: A parallel processing system or processor has a computing architecture including a plurality of execution units to repeatedly distribute instruction streams within the processor via corresponding buses, and a series of processing units to access the buses and selectively execute the distributed instruction streams. The execution units each retrieve an instruction stream from an associated memory and place the instruction stream on a corresponding bus, while the processing units individually may select and execute any instruction stream placed on the corresponding buses. The processing units autonomously execute conditional instructions (e.g., IF/ENDIF instructions, conditional looping instructions, etc.), whereby an enable flag within the processing unit is utilized to indicate occurrence of conditions specified within a conditional instruction and control selective execution of instructions in response to occurrence of those conditions. An enable stack is utilized to facilitate processing and execution of nested conditional instructions by storing the states of the enable flag for each nested conditional instruction. The parallel processor may further delay placement of selected instruction streams onto corresponding buses until each processing unit selecting a particular instruction stream enters a state to execute that instruction stream. In addition, each execution unit may cease placing an instruction stream onto a corresponding bus in response to no processing units selecting that instruction stream for execution.

Abstract: A 60-mW MPEG4 video codec has been developed for mobile multimedia applications. This codec supports both the H.263 ITU-T recommendation and the simple profile of MPEG4 committee draft version 1 released in November 1997. It is composed of a 16-bit reduced instruction set computer processor and several dedicated hardware engines so as to satisfy both power efficiency and programmability. It performs 10 frames/s of encoding and decoding with quarter-common intermediate format at 30 MHz. Several innovative low-power techniques were employed in both architectural and circuit levels, and the final power dissipation is 60 mW at 30 MHz, which is only 30% of the power dissipation for a conventional CMOS design. The chip was fabricated in a 0.3-/spl mu/m CMOS with double-well and triple-metal technology. It contains 3 million transistors, including a 52-kB on-chip SRAM. Internal supply voltages of 2.5 and 1.75 V are generated by on-chip dc-dc converters from 3.3-V external supply voltage.

Abstract: A computer configured to authenticate a user to an electronic transaction system is disclosed. The computer includes a central processing unit and electronic authorization firmware disposed within the computer and in electronic communication with the central processing unit. The electronic authorization firmware includes a non-volatile memory circuit configured to store at least one of a user private key and user identification data and a firmware identification data. The electronic authorization firmware further includes decryption logic circuitry disposed between the non-volatile memory circuit and the electronic transaction system. The decryption logic circuitry is configured to prevent unauthorized access to at least one of the user private key and the user identification data in the non-volatile memory circuit. The electronic authorization firmware also includes encryption logic circuit coupled to the electronic transaction system and configured to transmit digital data encrypted using the user private key for transmission to the electronic transaction system. The digital data authenticates the user to the electronic transaction system, wherein the non-volatile memory is inaccessible by the central processing unit without traversing the decryption logic circuitry.

Abstract: A 60-mW MPEG4 video codec has been developed for mobile multimedia applications. This codec supports both the H.263 ITU-T recommendation and the simple profile of MPEG4 committee draft version 1 released in November 1997. It is composed of a 16-bit reduced instruction set computer processor and several dedicated hardware engines so as to satisfy both power efficiency and programmability. It performs 10 frames/s of encoding and decoding with quarter-common intermediate format at 30 MHz. Several innovative low-power techniques were employed in both architectural and circuit levels, and the final power dissipation is 60 mW at 30 MHz, which is only 30% of the power dissipation for a conventional CMOS design. The chip was fabricated in a 0.3- m CMOS with double-well and triple- metal technology. It contains 3 million transistors, including a 52-kB on-chip SRAM. Internal supply voltages of 2.5 and 1.75 V are generated by on-chip dc-dc converters from 3.3-V external supply voltage.

Abstract: A computer system implementing a fault detection and isolation technique that tracks failed physical devices by identification (ID) codes embedded in each component of the computer for which the ability to detect faults and isolate failed devices is disclosed. The computer system comprises one or more CPU's, one or more memory modules, a master control device, such as an I2C master, and a North bridge logic device coupling together the CPU's, memory modules, and master control device. The master control device also connects to the CPU's and memory modules over a serial bus, such as an I2C bus. Each CPU and memory module includes an ID code that uniquely identifies and distinguishes that device from all other devices in the computer system. The computer also includes a non-volatile memory device coupled to the CPU for storing a failed device log which includes a list of ID codes corresponding to failed physical devices. After a device is determined to be non-functional, one of the CPU's stores that device's unique ID code in the failed device log. Using the list of physical devices from the failed device log, the CPU creates a logical resource map which includes a list of logical addresses of all available (i.e., fully functional) devices. The logical resource map is provided to the computer's operating system which isolates failed devices by only permitting access to those logical devices listed as available in the logical resource map.

Abstract: A first computer system (10) communicates with a second computer system (11) by way of a communication link (12). The first computer system (10) includes a central processing unit (1) with I/O interfaces (1b) leading to a keyboard processor (2) with a key matrix interface array (3). System ID's, a static secret, and a dynamic secret are stored on the hard disk drive (5b) of the first computer system (10) and are moved to RAM (1d) by the processor (1a) when the originating and answering stations are being authenticated.

Abstract: A system and technique facilitate fast context switching among processor complex stages of a pipelined processing engine. Each processor complex comprises a central processing unit (CPU) core having a plurality of internal context switchable registers that are connected to respective registers within CPU cores of the pipelined stages by a processor bus. The technique enables fast context switching by sharing the context switchable registers between upstream and downstream CPUs to, inter alia, force program counters into the downstream registers. In one aspect of the inventive technique, the system automatically reflects (shadows) the contents of an upstream CPU's context switchable registers at respective registers of a downstream CPU over the processor bus. In another aspect of the invention, the system redirects instruction execution by the downstream CPU to an appropriate routine based on processing performed by the upstream CPU.

Abstract: Internal variables generated by a compiler are assigned to machine resources such as registers and memory by the resource assigning unit 11, and when the assembler code generation unit 18 has outputted an instruction sequence, the alias accessibility analyzing unit 19 registers memory access instructions in the instruction sequence in the assigned resource information 14 according to whether the instructions have a possibility of access by alias. The assembler code optimization unit 20 refers to the assigned resource information 14 and performs optimization at assembler level, thereby reducing the program size and execution time of the instruction sequence.

Abstract: To suitably distribute the load between a client node and a server node in a client-server system, the client node sends a task request signal to the server node in response to input from a user. The server node, upon receiving the task request signal, acquires a CPU load ratio from the operating system and performs the requested task when the CPU load ratio is lower than a preset value to send the result of the task to the client node. Conversely, when the CPU load ratio is higher than the preset value, the server node sends a response signal to the effect that the client node is to execute the requested task. When the client node requests transmission of an application program in response to the response signal from the server, the server node sends an application program for use in performing the requested task to the client node. The client node executes the application program and obtains the result of the task.

Abstract: Synchronized execution is maintained by compute elements processing instruction streams in a computer system including the compute elements and a controller. Each compute element includes a clock that operates asynchronously with respect to clocks of the other compute elements. Each compute element processes instructions from an instruction stream and counts the instructions processed. Upon processing a quantum of instructions from the instruction stream, the compute element initiates a synchronization procedure and continues to process instructions from the instruction stream and to count instructions processed from the instruction stream. The compute element halts processing of instructions from the instruction stream after processing an unspecified number of instructions from the instruction stream in addition to the quantum of instructions. Upon halting processing, the compute element sends a synchronization request to the controller and waits for a synchronization reply.

Abstract: The Texas Instruments VelociTI architecture is a very long instruction word (VLIW) architecture. The TMS320C6x family of digital signal processors (DSPs) is the first to employ the VelociTI architecture, with the TMS3206201 (C6201) being the first device in this family. The C6201 is based on the fixed-point TMS320C62x (C62x) CPU. This article describes the VelociTI VLIW architecture and discusses the C62x, C67x, C6201, and the VelociTI development tools. An overview of the VelociTI including architectural principles, data path, instruction set, and pipeline operation is presented, and both the C62x fixed-point CPU and the C67x floating-point CPU are described. A summary of the C62x benchmark performance is also presented. The chip-level support outside the CPU that allows the C6201 to operate in a variety of high-performance DSP environments is also described. An overview of the C6x development environment is also given, demonstrating the breadth of the development environment and illustrating the programming methodology. The article concludes with a performance analysis of the C compiler.

Abstract: A computer system is provided with a dynamically reconfigurable boot order. In one embodiment, the computer comprises a user input device, a nonvolatile memory, a network interface, a boot trigger, and a CPU. The CPU is coupled to the user input device to detect a predetermined key press, coupled to the boot trigger to detect the assertion of a system reset signal, and coupled to the nonvolatile memory to retrieve a system BIOS in response to assertion of the system reset signal. The CPU executes the BIOS to initialize the computer system, and as part of the system initialization, the CPU determines a first target boot-up device. Preferably if the predetermined key has been pressed during the system initialization, the CPU alters the default boot order to select the network interface as the first target boot up device. The network interface is configurable to retrieve an operating system from a network device for the CPU to execute. The disclosed embodiment advantageously provides for reduced system installation and maintenance effort, and thereby lead to reduced costs for owners of computer networks.

Abstract: A method and apparatus for enhancing computer security while controllably enabling online remote access for power-up to a computer at a far cite and also offering functions adaptable for communication protocols accommodating network architecture. To this end, a remote network device is provided which includes a switch module on the power supply line coupled to a CPU and to more than one personal computer (PC) hardware resource connected to the CPU. The switch module is operable to switch the operation voltages of the CPU and hardware resources. The device also includes a stand-by module on a signal transmit/receive line for use with the CPU and PC hardware resources in transmitting and receiving signals to and from external communication facility associated therewith. The standby module comes with its own drive power supply independent of the PC's power supply, and is normally rendered operative in any communication events. The standby module includes an identifier unit and controller. The identifier is for identifying one or both of ID data and password involved in an externally supplied signal to provide identification (ID) data. The controller is responsive to this ID data for controlling switching operations of the switch module.

Abstract: The present invention provides a Wire Harness System method. This method is for aiding in the manufacture, repair, and testing of wire harnesses, wherein the method is run on a computer processor. The method further operates in a data acquisition mode and a display mode.

Abstract: A digital signal processing system comprising a central processing unit core (2), a memory (8) and a coprocessor (4) operates using coprocessor memory access instructions (e.g. LDC, STC). The addressing mode information within these coprocessor memory access instructions (P, U, W, Offset) not only controls the addressing mode used by the central processing unit core (2) but is also used by the coprocessor (4) to determine the number of data words in the transfer being speficied such that the coprocessor (4) can terminate the transfer at the appropriate time. Knowledge in advance of the number of words in a transfer is also advantageous in some bus systems, such as those that can be used with synchronous DRAM. The offset field within the instruction may be used to specify changes to be made in the value provided by the central processing unit core (2) upon execution of a particular instruction and also to specify the number of words in the transfer. This arrangement is well suited to working through a regular array of data such as in digital signal processing operations. If the Offset field is not being used, then the number of words to be transferred may default to 1.

Abstract: When a digitally compressed and encoded video data stream contains line data, a line data detection circuit in a DVD decoder detects the presence of that line data, and informs a CPU of it using an interrupt signal. When the CPU receives the line data from a data register in the DVD decoder, it converts it into character information and writes the information in an image memory, or converts the line data into an on-screen display command for controlling the OSD function of the DVD decoder and issues that command.

Abstract: A clock control type information processing apparatus of the invention selects clock frequency according to load state, which reduces electric power consumption without substantially reducing the effective performance of the program. The clock control type information processing apparatus including a central processing unit for executing programs and a plurality of peripheral processing units connected to the central processing unit using a bus, includes a clock generating unit for generating clock signals having a plurality of frequencies and selectively supplying any one of the clock signals to the central processing unit and the peripheral processing units, a bus access monitoring unit for monitoring load state of the bus which connects the central processing unit with the peripheral processing units; and a clock selection control unit for generating control signals to control the clock frequencies generated by the clock generating unit according to the load state of the bus.

Abstract: The present invention discloses a method of controlling the interaction of a host CPU ( 202 ) and at least one co-processor ( 224 ) in a computer system ( 201 ) to permit substantially simultaneous decoupled execution of CPU instructions and co-processor instructions. The co-processor instructions to be executed, and those which have been executed are allocated to respective queues ( 1040, 1041 ). From time to time the latter queue ( 1041 ) is cleaned up under control of the CPU ( 202 ) to release memory resources previously allocated to the co-processor by the CPU. This dynamic memory management arrangement preferably includes an instruction generator ( 1030 ), a memory manager ( 1031 ) and a queue manager ( 1032 ).

Abstract: Multi-channel Electronic Program Guide acquisition and soft picture-in-picture system for use with digital television receiver. The digital television receiver uses its central processing unit (CPU) to perform a software decode of packets received from a main tuner and/or a picture-in-picture. This allows the CPU to display video from pictures within the same RF channel or within another channel simultaneously with video information decoded in real-time by a hardware decoder. Also, in the case of a digital television with two tuners, the CPU can acquire and accumulate EPG data from multiple channels.

Abstract: A method and apparatus for providing an integral computer and telephone system includes a CPU, a telephone line interface operatively linked to the CPU, and a display device operatively linked to the CPU. Audio input and output devices are operatively linked to the CPU. A communication module for transceiving wireless signals is operatively linked to a remote unit. The system includes a switching device connected to the CPU and the communication module, where the switching device provides selective operation of the CPU and the remote unit, whereby when a user selects remote unit telephony, the remote unit substantially increases privacy and facilitates portability via wireless operation while when the user selects telephony via the CPU, the CPU facilitates both audio and visual information exchange.

Abstract: An integrated CPU has an on-board switching voltage regulator with an electrically-erasable programmable read-only memory electronically accessible for storing a feedback reference coefficient for control. In further embodiments, output voltage is tuned via a second EEPROM storing an electronically accessible value in concert with a solid-state resistor ladder. In other embodiments, signals on interrupt lines to the CPU are monitored to provide a prewarning of impending activity by the CPU requiring dramatically increased current flow. In yet other embodiments, solid state circuitry is provided to reduce or eliminate capacitors used for dealing with input current surges to the CPU.

Abstract: A processor complex architecture facilitates accurate passing of transient data among processor complex stages of a pipelined processing engine. The processor complex comprises a central processing unit (CPU) coupled to an instruction memory and a pair of context data memory structures via a memory manager circuit. The context memories store transient “context” data for processing by the CPU in accordance with instructions stored in the instruction memory. The architecture further comprises data mover circuitry that cooperates with the context memories and memory manager to provide a technique for efficiently passing data among the stages in a manner that maintains data coherency in the processing engine. An aspect of the architecture is the ability of the CPU to operate on the transient data substantially simultaneously with the passing of that data by the data mover.

Abstract: A data processing system, circuit arrangement, integrated circuit device, program product, and method dispatch multiple copies of a producer instruction to multiple execution units in a processor whenever it is determined that the producer instruction has or is likely to have multiple consumer instructions that are dependent on the producer instruction. Thus, when the multiple consumer instructions are subsequently dispatched to the multiple execution units, the results of the producer instruction are available within those execution units, and without the necessity for any inter-execution unit or inter-microcluster result forwarding. The decision of whether to dispatch multiple copies of a producer instruction may be made at runtime, e.g., within the dispatch unit of a processor, or in the alternative, may be made during compilation of a computer program to be executed on a multi-execution unit processor.

Abstract: Before a register provided exclusively for an Advanced Configuration and Power Interface (ACPI) is set, a System Management Interrupt (SMI) is issued to a Central Processing Unit (CPU). A System Management-Basic Input Output System (SM-BIOS) performs the power management of a computer system. Values representing a wakeup factor of the system and a power management event are set in the register, and an Operating System Directed Power Management System (OSPM) is informed of a Power Management Event (PME). When the values are set in the register, an SMI is issued to the CPU, and the SM-BIOS performs the power management of the computer system.

Abstract: A method of scheduling program instructions for execution in a computer processor comprises fetching and holding instructions from an instruction memory and executing the fetched instructions out of program order. When load/store order violations are detected, the effects of the load operation and its dependent instructions are erased and they are re-executed. The load is associated with all stores on whose data the load depends. This collection of stores is called a store set. On a subsequent issuance of the load, its execution is delayed until any store in the load's store set has issued. Two loads may share a store set, and separate store sets are merged when a load from one store set is found to depend on a store from another store set. A preferred embodiment employs two tables. The first is a store set ID table (SSIT) which is indexed by part of, or a hash of, an instruction PC. Entries in the SSIT provide a store set ID which is used to index into the second table, which for each store set, contains a pointer to the last fetched, unexecuted store instruction.

Abstract: This paper describes the 300-MHz StrongARM 1500 microprocessor, which is capable of more than two billion 16-b operations per second. Starting with the original StrongARM 110 design, an attached media processor (AMP) has been integrated along with a synchronous DRAM memory controller and separate I/O bus. In addition, several enhancements have been made to the CPU and cache subsystem, and the chip has been shrunk from a 0.35-to a 0.28-/spl mu/m technology. The chip includes 3.3 million transistors and measures 60 mm/sup 2/. It dissipates less than 3 W at 300 MHz at 2.0-V internal, 3.3-V I/O. The chip supports dynamic clock frequency switching for reduced operating power during low performance demands. There are 333 separately conditioned clocks on the chip, For battery-powered applications, V/sub dd/ can be reduced to achieve <0.5 W operation at 150 MHz. The chip is pseudostatic and can support clock stop and quiescent supply current testing. It implements the ARM V4 instruction set [1].

Abstract: A modular integrated apparatus and method that integrates mechanical, electrical, and thermal management, and that includes a computer processor (CPU), or VLSI module, connected to a circuit board and a thermal plate. The modular integrated apparatus includes a field replaceable apparatus and a receiving apparatus and attenuates EMI. By integrating mechanical, electrical, and thermal management features the modular integrated apparatus improves the process of repairing and upgrading the processor at a customer site by simplifying the modular integrated apparatus package. Additionally, by reducing the number of parts and the amount of circuit board space required to connect a processor to a thermal plate, the present embodiment improves ease of use and acts as a handle in its own installation and removal. Further, by including the processor and a heat sink in the field replaceable apparatus, the field replaceable apparatus reduces handling in the field and the risk of damage to the processor, and may be tested prior to installation in the field to ensure it operates properly.