Abstract: Proposes a method for compressing programs in embedded processors where the instruction memory size dominates the cost. A post-compilation analyzer examines a program and replaces common sequences of instructions with a single instruction codeword. A microprocessor executes the compressed instruction sequences by fetching codewords from the instruction memory, expanding them back to the original sequence of instructions in the decode stage, and issuing them to the execution stages. We apply our technique to the PowerPC, ARM and i386 instruction sets and achieve an average size reduction of 39%, 34% and 26%, respectively, for SPEC CINT95 programs.

Abstract: A computer system employing an instruction tracing mechanism includes a memory and a CPU. The memory includes a trace buffer used to store records of the instruction tracing. Entries in the trace buffer are pointed to by a tracer pointer. The memory is coupled to the CPU via a bus interface unit. Instructions are passed from the memory to the CPU via the bus interface unit and are queued in an instruction cache, which includes a byte queue. The CPU further includes a control unit coupled to a control register, the tracer pointer and a maskable ROM. The control unit controls and activates the instruction tracing mechanism. In response to software sitting a bit in the control register, the control unit functions to retrieve a special tracing microcode sequence from MROM to provide a trace record of the instructions as they are passed to the instruction decoders. A counting mechanism may also be activated to count instructions and store the count in the memory. The computer system further includes a register file coupled to the instruction decoders and functional units, also coupled to instruction decoders, to receive and process the instructions.

Abstract: A programmable gate array (FPGA) comprises a CPU coupled to a configuration memory array. Bitstream data used for configuring the configuration memory array is encoded to combine programming instructions and configuration data. The CPU receives and decodes the encoded bitstream data, and executes the programming instructions to efficiently load configuration data into the configuration memory array. For instance, configuration data can be temporarily stored in the CPU and reused where data patterns in the configuration memory array repeat. Use of the programmable CPU for loading the configuration memory array reduces the amount of data transmitted to the FPGA during array configuration.

Abstract: A multithreaded processor for executing multiple instruction streams is provided. This multithreaded processor includes: a plurality of functional units for executing instructions; a plurality of instruction decode units, corresponding to the multiple instruction streams on a one-to-one basis, for respectively decoding an instruction, and producing an instruction issue request for designating to which functional unit the decoded instruction should be issued and requesting for the issuance of the decoded instruction to the designated functional unit; a holding unit for holding the priority level of each instruction stream; and a control unit for deciding which decoded instruction should be issued to a functional unit designated by two or more instruction issue requests at the same time, in accordance with the priority levels held by the holding unit.

Abstract: Current research in compiler optimization counts mainly CPU time and perhaps the first cache level or two. This view has been important but is becoming myopic, at least from a system-wide viewpoint, as the ratio of network and disk speeds to CPU speeds grows exponentially.For example, we have seen the CPU idle for most of the time during paging, so compressing pages can increase total performance even though the CPU must decompress or interpret the page contents. Another profile shows that many functions are called just once, so reduced paging could pay for their interpretation overhead.This paper describes:• Measurements that show how code compression can save space and total time in some important real-world scenarios.• A compressed executable representation that is roughly the same size as gzipped x86 programs and can be interpreted without decompression. It can also be compiled to high-quality machine code at 2.5 megabytes per second on a 120MHz Pentium processor• A compressed "wire" representation that must be decompressed before execution but is, for example, roughly 21% the size of SPARC code when compressing gcc.

Abstract: A central processing unit (2) and a debug module (10) execute concurrent operations without requiring a data processor (3) to operate in a special debug mode. The use of a bus (25) to communicate data, address, and control information between a core (9) and debug module (10) allows debug module (10) to have access the same internal registers and memory locations as central processing unit (2). While debug module (10) and central processing unit (2) both have the ability to access the same internal registers and memory locations, central processing unit (2) may not modify a value stored in a plurality of breakpoint registers (50) when an Inhibit Processor Writes to Debug Registers (IPW) bit in a CSR (FIG. 8) of a plurality of control registers (40) is set. The IPW bit may only be modified by a command provided by an external development system (7).

Abstract: A user-removable CPU card includes a microprocessor and a bus bridge memory controller that allows the use of the microprocessor as a central processing unit of an electrical device (e.g. notebook PC or desktop PC). The user-removable CPU card includes a first connector that can be detachably coupled to a second connector in the electrical device, when the user-removable CPU card is inserted through an opening of the electrical device. When the electrical device is powered up subsequent to such insertion, the microprocessor on the user-removable CPU card functions as the central processing unit. Inclusion of a central processing unit of a computing device on a user-removable CPU card allows easy replacement of the CPU, for example, by simply opening a door and operating an eject mechanism, without disassembly of the housing. Therefore, a user can upgrade to a new central processing unit by simply ejecting a previously inserted user-removable CPU card and inserting a new user-removable CPU card, as easily as switching diskettes in the prior art (except for powering up the electrical device after such switching).

Abstract: In this paper, a neural network based approach to the electromagnetic (EM) simulation and optimization of high-speed interconnects is discussed. Traditional techniques used to model interconnects in high-speed very large scale integration (VLSI) circuits are based on EM-field simulation, and are thus highly demanding on central processing unit (CPU) resources. This limits their suitability for computer-aided design (CAD) and optimization techniques which are, in general, iterative in nature. Neural networks can be used to map the complex relationship between the physical and electrical parameters of interconnect structures in an efficient manner. The models, once developed, operate with minimal on-line CPU resources and are thus ideally suited for use in iterative CAD and optimization routines.

Abstract: Portable systems demand energy efficiency in order to maximize battery life. IRAM architectures, which combine DRAM and a processor on the same chip in a DRAM process, are more energy efficient than conventional systems. The high density of DRAM permits a much larger amount of memory on-chip than a traditional SRAM cache design in a logic process. This allows most or all IRAM memory accesses to be satisfied on-chip. Thus there is much less need to drive high-capacitance off-chip buses, which contribute significantly to the energy consumption of a system. To quantify this advantage we apply models of energy consumption in DRAM and SRAM memories to results from cache simulations of applications reflective of personal productivity tasks on low power systems. We find that IRAM memory hierarchies consume as little as 22% of the energy consumed by a conventional memory hierarchy for memory-intensive applications, while delivering comparable performance. Furthermore, the energy consumed by a system consisting of an IRAM memory hierarchy combined with an energy efficient CPU core is as little as 40% of that of the same CPU core with a traditional memory hierarchy.

Abstract: A computer-implemented method for executing a computer file in a CPU emulator (154) to detect a computer virus. The method includes simulating (302) the execution of a predetermined number of instructions of the computer file in the CPU emulator (154), suspending (303) the execution, constructing (304) a state record, temporarily storing (305) the state record in memory, comparing (306) the constructed state record to state records stored in a state cache (158), and indicating (308) that the file is virus free when the constructed state record matches one of the stored state records.

Abstract: A system and method for sending and receiving data with a reliable communication protocol. The system includes a computer at a node having a backplane, a CPU board plugged into the backplane, software instructions for the CPU, and a special network board plugged into the backplane. The CPU board, software, and network card act to implement the TCP/IP protocol suite. The network card or board includes an interface to receive data packets from the physical layer, and circuitry to verify the TCP checksum before de-encapsulation and routing of the TCP segment by the network layer software. It also includes circuitry to automatically prepare the acknowledgement signal to be sent by the receiving computer to the sending computer. It additionally includes circuitry to calculate the error detecting code on outgoing signals from the sending computer to the receiving computer.

Abstract: A method and apparatus for preventing system wide data dependent stalls is provided. Requests that reach the top of a probe queue and which target data that is not contained in an attached cache memory subsystem, are stalled until the data is filled into the appropriate location in cache memory. Only the associated central processor unit's probe queue is stalled and not the entire system. Accordingly, the present invention allows a system to chain together two or more concurrent operations for the same data block without adversely affecting system performance.

Abstract: A method, apparatus and computer program for controlling data migration in an information processing system which includes a central processing unit (CPU), a new storage system connected to the CPU and an old storage system connected to the new storage system. In the information processing system data migration is conducted to transfer data from the old storage system to the new storage system. The invention operates by permitting access by the CPU to the storage systems during data migration. When an access by the CPU is generated the invention determines whether the access is to a region where data migration has been completed or to a region where data migration has not been completed. If the access is to a region where data migration has been completed, then processing of the access is handled by the new storage system. If the access is to a region where data migration has not been completed, then processing of the access is handled by the old storage system causing data related to the access to be transferred from the old storage system to the new storage system. The speed of data migration can be adjusted based upon the utilization of the resources of the information processing system and information of the priority of access to the new storage system by the CPU.

Abstract: A dual instruction set processor decodes and executes code received from a network and code supplied from a local memory. Thus, the dual instruction set processor is capable of executing instructions in two different instructions sets from two different sources. The dual instruction set processor includes a computer platform independent instruction decoder, another decoder, and an execution unit that executes decoded instructions from both of the decoders. A computer system with the foregoing described dual instruction set processor, a local memory, and a communication interface device, such as a modem, for connection to a network, such as the Internet or an Intranet, can be optimized to execute, for example, JAVA code, in example of one set of computer platform independent instructions, from the network, and to execute non-JAVA code stored locally, or on the network but in a trusted environment or an authorized environment.

Abstract: An intelligent power strip circuit for providing automatic computer system power down features and for providing automatic restoration of power for the computer system. The intelligent power strip circuit may be used by conventional computer systems that do not have internal power management features to retrofit them to provide power conservation modes. The circuit is responsive to an incoming phone call and will provide automatic power on and system initialization to enable the computer system to respond to a call. The circuit is responsive to the keyboard, mouse, and other user interface devices (for automatic power up and conditional timed power off) because these devices are routed through the external circuit to the computer system. Peripherals and the CPU chassis of the computer system receive their AC power via the circuit and therefore may be automatically powered down under control of the CPU when appropriate. Programming logic operable on the computer system controls aspects of the power strip circuit. The circuit provides automatic power up features. The intelligent power strip is advantageously suited to provide power management features to conventional computer systems that were implemented before such features were widely available and internally installed. The circuit therefore provides power savings to a large number of computer systems.

Abstract: A novel apparatus and method is disclosed to decode an encoded MPEG video stream in an efficient manner making optimal use of available system memory and computational resources. The present invention partitions the MPEG video decode task into software tasks which are executed by a CPU and hardware tasks which are implemented in dedicated video hardware. Software tasks represent those tasks which do not require extensive memory or computational resources. On the other hand, tasks implemented in dedicated video hardware represent those tasks which involve computational and memory mintensive operations. Synchronization between software tasks executed by the CPU and hardware tasks implemented in dedicated video hardware is achieved by means of various data structures, control structures and device drivers.

Abstract: A computer processor complex including a hardware processor coupled to a multimedia coprocessor is provided. This computer processor complex is capable of separately processing a stream of non-multimedia instructions in addition to a stream of multimedia instructions such as are used in MPEG audio and video. The computer processor complex includes a visible register set including registers for a program counter and a data pointer. The program counter is used to hold the address in memory where the multimedia instructions are located and the data pointer indicates where the data, corresponding to these multimedia instructions, is located in memory. A hardware processor is coupled to a first bidirectional port on the visible register set and a multimedia coprocessor is coupled to a second bidirectional port on the visible register set. The bidirectional ports allow the hardware processor and the coprocessor to exchange data and status information typically using an interrupt based communication mechanism. A main memory device is also coupled to the hardware processor over bidirectional port and coupled to the multimedia processor over a second bidirectional port. This arrangement allows the hardware processor and the coprocessor to share main memory and load separate instruction streams from main memory.

Abstract: A method and apparatus for providing power management functions in a multifunction controller having an embedded microprocessor. An enter sleep mode indication is received in the microprocessor in the form of, for example, a command generated by a host central processing unit or an interrupt indicating a lack of system activity for a predetermined period of time. The clock input to the microprocessor is switched from a first clock source to a second clock source in response to the enter sleep mode indication. The main system supply may then be powered down by the microprocessor. The first clock source is then turned off after expiration of a first predetermined delay. The second clock is subsequently turned off after a second predetermined delay, to thereby place the system and the microprocessor into a sleep mode. While the system and microprocessor are in the sleep mode, an interrupt-handling portion of the microprocessor and a power control logic circuit remain powered off a low-current standby supply. Upon detection of a wake-up event, the second clock source is automatically started and applied to the microprocessor after a predetermined delay. The microprocessor can then process the wake-up event indicator, and if necessary power up the system and re-connect itself to the first clock source.

Abstract: A combined remote access and security system for servicing a secure mainframe central processing unit having a console monitor. A secure dispatch central processing unit for receiving problem reports concerning the mainframe central processing unit is in communication with the console monitor. A field engineer's central processing unit is in communication with the dispatch central processing unit. A data encryption key is randomly generated and transmitted from the dispatch central processing unit to both the field engineer's central processing unit and the console monitor. The field engineer central processing unit is in communication with the mainframe central processing unit wherein data transmitted from the field engineer's central processing unit is encrypted and wherein the encrypted data is decrypted at the mainframe console monitor.

Abstract: A method for forwarding operands directly between instructions operates in a computer central processing unit. Values for registers, condition codes, stack locations and memory storage locations are routed directly from the program instructions or microcode that alter them to the instructions that use those operands. Instructions that have received all needed operands are started and their resulting output operands are forwarded to other instructions. With direct forwarding of operands, normal locations for operands may often be skipped so that simpler designs can be employed in constructing the operand storage for register files and stacks. Operands receiving newer values never appear in program-visible locations if the prior values were forwarded to all instructions that might need them and those receiving instructions are completed. In executing program loops, loop-dependent variables are identified. A method is shown whereby multiple loop-dependent operands are computed substantially simultaneously. In favorable circumstances multiple iterations of one or more loops are executed in parallel. The number of iterations is computed and then governs the number of loop iterations executed. Storage of results in architected, generally available areas is avoided where operands are no longer needed after loop iteration execution.

Abstract: A communication system comprising a plurality of network elements and a monitoring apparatus for centrally monitoring and controlling these network elements. Each of the network elements has a plurality of CPU's and a flash memory for accommodating programs to be performed by the CPU's. The monitoring apparatus includes a database, a management unit and a transfer unit. The database retains a plurality of programs for each of the CPU's in each network element, and generic issues defined uniquely corresponding to combinations of versions of programs to be executed by each CPU. When the version of any program is changed, the management unit selects the program to be transferred in accordance with the applicable generic issue. The transfer unit transfers the program thus selected to the monitoring apparatus.

Abstract: A networked sensor system that simultaneously acquires, processes, and transmits sensor data under the control of a central processing unit. The system includes sensors connected to sensor processing modules. The sensor processing modules are serially coupled together and to the central processing unit by a fiber optic network. The central processing unit can change the sensor sampling rate by changing a global clock rate, can describe the number and layout of sensor processing modules and their associated sensors allowing for reconfiguration in accordance with a desired application, and can download code to the sensor processing modules for modifying processing functions for a given application. The global clock also allows for synchronous sampling throughout the network. Sensor gain in the sensor processing modules is dynamically programmed by the central processing unit.

Abstract: A processor having a large register file utilizes a template field for ening a set of most useful instruction sequences in a long instruction word format. The instruction set of the processor includes instructions which are one of the plurality of different instruction types. The execution units of the processor are similarly categorized into different types, wherein each instruction type may be executed on one or more of the execution unit types. The instructions are grouped together into 128-bit sized and aligned containers called bundles, with each bundle includes a plurality of instruction slots and a template field that specifies the mapping of the instruction slots to the execution unit types.

Abstract: An information processing system is connected to a common storage and executes programs by use of processors. This system includes a common storage; a plurality of processors, connected to the common storage. Each processor executes an instruction to store data from common storage, and an instruction to load data from the common storage into the cache storage, wherein each processor includes a communication controller for, when detecting synchronization completion information for attaining synchronization of execution of instructions among a plurality of processors, sending synchronization completion information and receiving synchronization information from another processor; an instruction executing section for detecting a specified change of the flag of a specified location in the common storage by executing a Monitor instruction included in a program in response to synchronization information from the communication controller; an execution controller to execute subsequent instructions after the Monitor instruction, exclusive of a Load instruction to load data into a cache storage, until a change of the flag is detected by the execution section, wherein the processor allows instruction for loading data from common storage into the cache storage to be executed after the flag detection, and wherein the execution controller may include an inhibit resetting circuit to issue an inhibit instruction control signal to terminate the instruction send-out inhibiting action of the instruction inhibit circuit according to input from a service processor.

Abstract: A computer-implemented apparatus and method for countering attempts of polymorphic viruses to evade detection by emulation-based scanners. Such attempts try to exploit differences between the real and virtual execution of instructions. The invention includes a fault manager (158) integrated into the CPU emulator (154) of a virus scanner software product. Before each instruction is emulated by the CPU emulator (154), the fault manager (158) examines the opcode of the instruction to determine (310) whether a "fault" is triggered. If a fault is triggered, the fault manager (158) saves (314) a state record on a fault stack (162), then interrupts (316) to a corresponding fault handler routine (160). The criteria for triggering a fault and the corresponding fault handler routine (160) may be obtained from an updatable data file (164).

Abstract: A battery-powered computing system (20) including video decoding capability, particularly as pertinent to the H.263 standard, is disclosed. The system (20) includes a main integrated circuit (30) having an on-chip central processing unit (CPU) (32) and on-chip shared memory (33) for the temporary buffering of video image data that is retrieved and generated during the video decoding process. The CPU (32) is programmed to perform a combined P and B prediction process (46) upon a previously predicted P frame (PT-1), with accesses to internal buffers in shared memory (33) instead of to main memory (40). Preferably, inverse transform processes (48, 52) also access shared memory (33) rather than main memory (40). The combined P and B prediction process (46) preferably handles unrestricted motion vectors using edge pixels (Pedge) stored in an edge buffer (44e) in the on-chip memory (33), by modifying (58, 60) motion vector components (MVx, MVy) that point outside of the displayable video image, and retrieving the corresponding edge pixels (Pedge) from the edge buffer (44e) in this event. The on-chip memory (33) preferably also includes a buffer (NEWBFR) for storing current predicted P blocks, such that the previous predicted P frame (PT-1) and the current predicted P frame (PT) can share the same memory space (old/newframe). The power requirements of the video decoding process are thus much reduced, as memory accesses to large, off-chip, main memory (40) are limited.

Abstract: A multi-function device has a user interface with two buttons that are operated using a two-button protocol to generate function messages and instruction messages. Each function message identifies or describes one of the different functions of the device, while each instruction message corresponds to one of the instruction steps for one of the device functions. The user interface generates signals to control presentation of the function and instruction messages. The device also has a message processor that generates the function and instruction messages based on the signals from the user interface as well as a message rendering component to render the function and instruction messages. In one embodiment, the various function and instruction messages are audio messages and the message rendering component is a speaker, although other, non-visual messages could be used instead. The message processor may be implemented as part of a single chip processor that has an input-output component, a data memory component, and a central processing unit. In addition to instruction and function messages, the two-button user interface can be used to generate troubleshooting messages.

Abstract: The invention is a system providing adaptive stream buffers using instruction-specific prefetching avoidance (ISPA). According to the invention, each time the CPU executes an instruction resulting in prefetched cache lines not being used, the instruction address is stored in a table. Subsequent instruction addresses are compared to the instruction addresses in the table, and a stream buffer is not allocated when the subsequent instruction address is found within the table.

Abstract: A method is presented for event-related functional testing of a microprocessor. A model of the microprocessor is adapted to produce a trigger event, perform a target activity, and respond to a control signal. The target activity occurs over several system clock signal cycles. A control signal generator receives the trigger event and generates the control signal a selectable number of clock cycles (i.e., a delay time) after the trigger event. A testing program includes a program loop which causes the microprocessor model to produce the trigger event, perform the target activity to produce a test result, and compare the test result to an expected result. The program loop is repeatedly executed until the microprocessor model responds to the control signal during each clock cycle of the target activity. If the test result matches the expected result during each execution of the program loop, the microprocessor properly responds to the control signal during the target activity. The microprocessor model may be a software or hardware implementation. Software embodiments of a bus model, a memory model, and a test engine provide an operating environment for the microprocessor model. A microprocessor testing system includes a central processing unit (CPU), chip set logic, a system bus, a memory bus, and a memory unit. In a first embodiment of the testing system, the microprocessor model, the bus model, the memory model, and the test engine reside within the memory unit. In a second embodiment, the microprocessor model is a separate hardware implementation.