Abstract: A portable image transfer system includes a digital still camera which captures images in digital form and stores the images in a camera memory, a cellular telephone transmitter, and a central processing unit (CPU). The CPU controls the camera memory to cause it to output data representing an image and the CPU controls the cellular telephone transmitter to cause a cellular telephone to transmit the data received from the camera memory. A receiving station is coupled to the cellular telephone transmitter by a cellular network to receive image data and store the images.

Abstract: An ultrasonic diagnostic imaging system is provided with a personal computer platform which processes digital echo signals and produces ultrasonic image signals for display. The expansion bus structure of the personal computer platform accommodates ancillary processors such as beamformer cards, digital signal processing cards, video cards, and network cards which may be necessary or desirable for the ultrasound system. In a preferred embodiment the digital signal samples produced by a beamformer connected to the expansion bus are processed for display by software executed by the CPU of the personal computer platform. A preferred software architecture for the personal computer based ultrasound system consists of multiple object oriented software tasks, executing under a realtime, multitasking operating system which is both efficient and robust. Performance upgrades of the entire ultrasound system are effected by simple replacement of the CPU with a higher performance CPU, thus providing continual ultrasound system performance improvements in consonance with the evolution of personal computer CPU technology.

Abstract: In a microcomputer comprising internal buses (AB, DB) , a serial communication interface (2), a flash memory (4) , a RAM (5), a ROM (6) for storing a writing program, an input/output port (1b), a CPU (7), and a mode control unit (3) for setting various operation modes and test modes in the microcomputer, a switching circuit (8) is connected between the ROM and the internal buses and between the input/output port and the internal buses. The mode control unit operates the switching circuit in an emulation test mode so that the ROM is deactivated and the input/output port is activated. Then, the CPU reads a program from the serial communication interface and writes the program into the flash memory in accordance with a writing program from the input/output port.

Abstract: A data processing system (100) includes a data processor or CPU (102) having decompression circuitry (208, 212) and decryption circuitry (210, 214) that operates on compressed/encrypted data to produce decompressed and decrypted data. The data processing system includes memory (104) in which instructions and data are stored in a compressed (110) and/or encrypted (114) format. The CPU (102) retrieves the compressed/encrypted data over a system bus (106). A bus interface unit (200) within the CPU (102) receives the compressed/encrypted data, decompresses and decrypts the data and stores the data in cache memory (202). An execution unit (204) and other components within the CPU (102) retrieve the decompressed and decrypted data and operate upon it. Alternatively, upon retrieval of compressed/encrypted data from memory (104) the data is stored in cache memory (202) in its compressed/encrypted format. Upon retrieval by the execution unit (204), the data is decompressed and decrypted in preparation for execution by the execution unit (204). A data processing system (400) of the present invention requires that the CPU (402) decrypt encrypted data. Thus, any devices accessing data in the system (400) over a network (426) without decryption by the CPU (402) retrieve encrypted data that cannot otherwise be decrypted.

Abstract: Instruction cache misses can severely limit the performance of both superscalar processors and high speed sequential machines. Instruction prefetch algorithms attempt to reduce the performance degradation by bringing lines into the instruction cache before they are needed by the CPU fetch unit. There have been several algorithms proposed to do this, most notably next line prefetching and target prefetching. We propose a new scheme called wrong-path prefetching which combines next-line prefetching with the prefetching of all control instruction targets regardless of the predicted direction of conditional branches. The algorithm substantially reduces the cycles lost to instruction cache misses while somewhat increasing the amount of memory traffic. Wrong-path prefetching performs better than the other prefetch algorithms studied in all of the cache configurations examined while requiring little additional hardware. For example, the best wrong-path prefetch algorithm can result in a speed up of 16% when using an 8 K instruction cache. In fact, an 8 K wrong-path prefetched instruction cache is shown to achieve the same miss rate as a 32 K non-prefetch cache. Finally, it is shown that wrong-path prefetching is applicable to both multi-issue and long L1 miss latency machines.

Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. The CPU comprises a memory for storing instructions and data; a pair of processors operating in lock-step synchronism with each other to execute each instruction of an instruction stream and to periodically write identical N-bit data words comprising first and second portions to the memory at substantially the same moment in time; first and second interface elements communicating the N-bit data words from corresponding ones of the pair of processors to the memory such that the first portion of the N-bit data word from a one of the pair of processors is written to the memory by the first interface unit together with the second portion of the N-bit data from the second interface element; the first interface unit including means for receiving comparing the second portion of the N-bit data word from the second interface unit with the second portion of the N-bit data word received from the corresponding one of the pair of processors to assert an error signal is a miscompare is detected; and the second interface unit including means for receiving comparing the first portion of the N-bit data word from the first interface unit with the first portion of the N-bit data word received from the corresponding one of the pair of processors to assert an error signal is a miscompare is detected.

Abstract: A data processing system for transferring data is provided. This system includes central processing units (CPUs 20, 22, 24 and 26) and storage units (30 and 32 with 100-105 and 110-115) which are interconnected by a network (10). The CPUs (20, 22, 24 and 26) include a request process (133) and a storage process (130). The storage process (130) controls access to the storage unit (30 with 100-105 and 110-115). Software routines (220) are used to provide direct access to the storage unit (30 with 100-105 and 110-115) by the request CPU (22). The request CPU (20) is the CPU containing the request process (133). A virtual memory address for a buffer (160) of the request CPU (22) is created in the request CPU (22). The virtual memory address along with a storage unit access request are sent to the CPU (20) containing the storage process (130). A work request including the virtual memory address to sent from the storage process (130) to the storage unit (30 with 100-105 and 110-115). The data is then transferred directly between the request CPU (22) and the storage unit (30 with 100-105 and 110-115). The storage unit (30 with 100-105 and 110-115) then responds to the work request.

Abstract: In a computer system the typically high overhead requirement for CPU instructions to operate a conventional direct memory access (DMA) controller are reduced to two user-level memory references via User-level Direct Memory Access (UDMA) The UDMA apparatus is located between the CPU and a DMA Controller, whereby the UDMA is programmed to use existing virtual memory translation hardware of the associated computer system to perform permission checking and address translation without Kernel involvement, and otherwise use minimal Kernel involvement for other operations

Abstract: This paper deals with automated test pattern generation for large synchronous sequential circuits and describes an approach based on genetic algorithms. A prototype system named GATTO is used to assess the effectiveness of the approach in terms of result quality and CPU time requirements. An account is also given of a distributed version of the same algorithm, named GATTO*. Being based on the PVM library, it runs on any network of workstations and is able to either reduce the required time, or improve the result quality with respect to the monoprocessor version. In the latter case, in terms of Fault Coverage, the results are the best ones reported in the literature for most of the largest standard benchmark circuits. The flexibility of GATTO enables users to easily tradeoff fault coverage and CPU time to suit their needs.

Abstract: A computer system includes a processor bus having processor data and processor check bits for performing error detection and correction of the processor data. A CPU is coupled to the processor bus. A memory sub-system is coupled to the processor bus and includes memory check bits, memory address bits, and memory data bits, and an error detection and correction device for detecting an error in the memory address bits using the memory check bits and for detecting an error in the memory data bits using the memory check bits. The CPU can include a processor from the Pentium® Pro family of processors. The error detection and correction device generates a syndrome table which includes a plurality of entries mapped to correctable or uncorrectable errors, in which a detected multiple-bit error in the memory data bits is mapped to an uncorrectable error entry and a detected error in the memory address bits is mapped to an uncorrectable error entry. An error detection device is also coupled to the processor bus for detecting an error in the address bits or data bits using the processor check bits.

Abstract: The image composition system includes a display device coupled to a central processing device for displaying a user selected image. A camera coupled to the central processing device enables a real subject to be incorporated into the user selected image. Accessory items are stored in a memory device coupled to the central processing unit for combining with the subject in the user selected image.

Abstract: Two cooling functions are provided: one being reduction in operation speed of a CPU, and the other being rotation of a motor fan. The two cooling functions are selectively used in accordance with a cooling mode set by a user. When a "Quiet" mode is selected by the user, a mode giving a priority to low power consumption is set to make the battery operation time as long as possible. In this case, the motor fan is not rotated and only the CPU operation speed is lowered. On the other hand, when a "Performance" mode is selected by the user, a mode giving a priority to performance is set. In this case, the CPU operation speed is not lowered, and only the motor fan is rotated. The "Performance" mode and "Quiet" mode can be freely set by the user on a setup screen.

Abstract: In the future, advanced integrated circuit processing and packaging technology will allow for several design options for multiprocessor microprocessors. In this paper we consider three architectures: shared-primary cache, shared-secondary cache, and shared-memory. We evaluate these three architectures using a complete system simulation environment which models the CPU, memory hierarchy and I/O devices in sufficient detail to boot and run a commercial operating system. Within our simulation environment, we measure performance using representative hand and compiler generated parallel applications, and a multiprogramming workload. Our results show that when applications exhibit fine-grained sharing, both shared-primary and shared-secondary architectures perform similarly when the full costs of sharing the primary cache are included.

Abstract: The security arrangement includes a computer processor unit coupled to a subscriber information memory to verify whether the user is an authorized user. The subscriber information memory stores subscriber voice information and variable security level information. A prompt memory coupled to the computer processor unit requests the user to input a set of verification information determined by the security level information. The input set of verification information is compared with stored subscriber voice information by a voice analyzer coupled to the subscriber information memory, wherein access to the system is enabled when the input set of verification information corresponds substantially with the subscriber voice information.

Abstract: A method and apparatus are provided for testing memory locations of embedded memories or on-board caches of a micro-controller, a micro-processor or a CPU-based integrated circuit through use of a test access port (TAP) such as the IEEE TAP described in "IEEE Standard Test Access Port and Boundary-Scan Architecture" (IEEE Std. 1149.1-1990). The TAP is utilized to serially shift address, data and command information provided by an external host into respective fields of a memory access register (MEMACC) located within a memory interface unit (MIU) of the CPU-based IC. Responsive to the command information, the TAP requests access to the IC's memory bus via the MIU. Next, the address, data and command information for accessing the embedded memory are serially shifted into the MEMACC. If a read operation is specified by the command information, the MIU returns the data stored in the specified memory location of the embedded memory and replaces the data within the data field of the MEMACC with the newly retrieved data. If a write operation is specified by the command information, the MIU transmits the data held in the data field of the MEMACC to the memory location specified. Finally, the data, address and command information stored in the MEMACC are serially shifted out via the TAP to the external host which analyzes the data output therefrom.

Abstract: An instruction cache design which converts a sequential instruction stream into a compound format in the instruction cache. The conversion from sequential instructions to compound instructions is performed by an instruction stream interpreter unit (ISU), which is placed between the instruction cache and main memory. The conversion process is performed when an instruction cache miss occurs. Each line in the instruction cache contains a single compound instruction. The format of this compound instruction is transparent to programmers and will vary depending on the number of execution units which are to be supported.

Abstract: A technique is provided for selecting a preferred thread from a plurality of threads executing within a simultaneous multithreaded, out-of-order execution computer system, the preferred thread possessing those instructions which, while in flight within the pipeline of the computer system provide, in contrast to those instructions belonging to other threads, a more beneficial performance of the central processing unit of the computer system. To determine the preferred thread, a technique is provided to evaluate attributes of each thread which indicate whether the thread includes a number of instructions which are likely to be cancelled while in flight or whether a thread includes instructions which will remain in the instruction queue for a number of cycles, unable to execute, thus stalling the execution of the thread to which the instruction belongs.

Abstract: A router is integrated onto a single silicon chip and includes an internal bus that couples multiple data receive and transmit channels to a central processing unit. The channels each have an external interface for connecting to different LAN or WAN networks. The serial channels are convertible into one or more time division multiplexed (TDM) channels. A time slot assigner (TSA) assembles and disassembles data packets transferred in TDM formats, such as ISDN. The serial channels are used for separately processing data packets in each TDM time slot. The TSA is programmable to operate with different TDM formats. A single direct memory access controller (DMAC) is coupled to each serial channel and an Ethernet channel and conducts data transfers on the internal router bus through a common port. The DMAC uses a novel bus protocol that provides selectable bandwidth allocation for each channel. The router architecture includes different interface circuitry which is also integrated onto the silicon chip. The interface circuitry includes user definable input/output (I/O) pins with programmable pulse width detection. The user definable I/O provides synchronous and asynchronous interfacing to peripheral devices with different timing constraints. The interface circuitry also includes a DRAM controller having a programmable timing control circuit that operates with memory devices having different timing and memory block sizes.

Abstract: The data processing system includes a plurality of execution units forming a plurality of processing pipelines. The plurality of processing pipelines process instructions and include a storage pipeline. The data processing system further includes an instruction unit and a storage control unit. The instruction unit outputs instructions to the plurality of execution units, and controls execution of multiple threads by the plurality of execution units. If an instruction for a first thread in the storage pipeline experiences a cache miss and the instruction unit decides to switch threads, the instruction unit begins processing a second thread. The instruction unit also issues a data request to the storage control unit to obtain the missing data. During processing of the second thread, unused slots will appear in the storage pipeline because it is not possible to always dispatch instructions to completely keep the pipelines filled. After the requested data returns from higher level memory, the storage control unit will dispatch the instruction from the first thread having received the cache miss to an unused slot in the storage pipeline. Consequently, this instruction from the first thread will be processed along with the instructions from the second thread.

Abstract: A method and apparatus for sequencing computer instructions in memory (24) to provide for more instruction efficient execution by a central processing unit (CPU) (22) begins by executing the computer instructions via the CPU (22) and creating a trace file (FIG. 2) in memory (24). The trace file is then scanned using a window size greater than two (i.e., more than two instructions or basic blocks/ groups of instructions are selected as each window) and correlations are determined between several pairs of instructions in each window (FIGS. 9 and 10). The correlations obtained by the window procedure are then analyzed (FIG. 11) to determine an efficient ordering of computer instructions for subsequent execution by any target CPU.

Abstract: A programmable DMA controller that uses an instruction set dedicated to moving data efficiently over a bus, comprising a program memory, a program counter, a FIFO memory, a bus buffer, registers, an accumulator, and an ALU. The DMA controller instruction set comprises the following instructions: load, move, add, subtract, branch on zero, branch on not zero, lock, and interrupt. Another DMA controller embodiment uses a SIMD processor. In operation, a CPU downloads DMA programs to the DMA controller. The DMA controller stores these programs in its program memory. The CPU signals the DMA to begin a DMA transfer operation. The ALU and associated devices execute the program instructions to perform the desired DMA transfer. The DMA controller then sends an interrupt to the CPU to indicate the DMA transfer is complete.

Abstract: A CPU or microprocessor which includes a general purpose CPU, such as an X86 core, and a DSP. The CPU also includes an intelligent DSP function decoder or preprocessor which examines X8 opcode sequences and determines if a DSP function is being executed. The function preprocessor includes a look-up table which stores instruction sequences which implement DSP functions. Each pattern in the look-up table is compared with an instruction sequence to determine if one of the patterns substantially matches the instruction sequence. If the DSP function preprocessor determines that a DSP function is being executed, the DSP function preprocessor converts the opcodes to a DSP macro instruction that is provided to the DSP. The DSP executes one or more DSP instructions to implement the desired DSP function in response to the macro instruction. If the X86 opcodes in the instruction cache or instruction memory do not indicate or are not intended to perform a DSP-type function, the opcodes are provided to the X86 core. Thus, the DSP offloads these mathematical functions from the X86 core, thereby increasing system performance. The DSP operates in parallel with the X86 core, providing further performance benefits. The CPU of the present invention thus implements DSP functions more efficiently than X86 logic while requiring no additional X86 opcodes. The present invention also generates code that operates transparently on an X86 only CPU or a CPU according to the present invention which includes X86 and DSPs. Thus the present invention is backwards compatible with existing software.

Abstract: One or more machine code entities such as functions are created which represent solutions to a problem and are directly executable by a computer. The programs are created and altered by a program in a higher level language such as "C" which is not directly executable, but requires translation into executable machine code through compilation, interpretation, translation, etc. The entities are initially created as an integer array that can be altered by the program as data, and are executed by the program by recasting a pointer to the array as a function type. The entities are evaluated by executing them with training data as inputs, and calculating fitnesses based on a predetermined criterion. The entities are then altered based on their fitnesses using a machine learning algorithm by recasting the pointer to the array as a data (e.g. integer) type. This process is iteratively repeated until an end criterion is reached. The entities evolve in such a manner as to improve their fitness, and one entity is ultimately produced which represents an optimal solution to the problem. Each entity includes a plurality of directly executable machine code instructions, a header, a footer, and a return instruction. The alteration process is controlled such that only valid instructions are produced. The headers, footers and return instructions are protected from alteration. The system can be implemented on an integrated circuit chip, with the entities stored in high speed memory in a central processing unit.

Abstract: A computer system includes an operator input device, a central processing unit (CPU), and a display device, such as a liquid crystal display (LCD) or cathode ray tube (CRT) providing a visible image to the computer user as an output of computer activity. The computer system includes a video display controller (VDC) with a graphics generator. This VDC receives image information, such as text or graphics generated by the CPU, or retrieved by the CPU from another facility (such as a CD-ROM) of the computer system, and responsively provides image signals driving the CRT or LCD display. The VDC includes a power saving controller implementing one of several available power saving modes dependent upon one or more of several possible inputs. Each of the power saving modes includes the same list of VDC functions which may individually be enabled or disabled in each power saving mode dependent upon a bit value entered into a register of the power saving controller. Each of the power saving modes is ranked with the others in an order of succession. Accordingly, when each mode of power saving is enabled, it disables the lower-ranked modes of power saving. In turn, each mode of power saving is disabled and succeeded if a higher-ranked mode is enabled.

Abstract: A method for reducing power consumption in a computer system is provided wherein the computer system includes a system bus interface connected by a signal line to a power supply and/or clock circuitry for the central processing unit, each having the capability to change the characteristic of its output responsive to the signal line for placing the central processing unit in a low-power consuming state. The system bus interface chip further including a storage location and counter for storing the type and quantity of interrupt assertions during the period of time when the central processing unit is in the low power consuming state. The system software determines the desired period of time to put the central processing unit into the low-power consuming state and does not return it to normal power consuming state until the time period has expired, a non interval clock interrupt is asserted, or another critical event occurs that needs immediate CPU attention. When one of these conditions arises, the signal line changes polarity, the power supply and/or clock circuitry returns normal operating levels to the CPU, and the system bus interface presents all interrupts that asserted while the CPU was in the low-power consuming state to the CPU so it can continue normal operation.

Abstract: An apparatus (101) and method for interfacing between a processor (103) and a communications channel (105), the processor operable in data terminal equipment (102) such as a computer having a communications application program, to provide for data transmission and reception over a communications channel (105), utilizing the computer processor without additional or redundant microprocessor or digital signal processor components. The apparatus and method provide for data transfer between the interface apparatus (101 ) and the communications channel (105) at a first, determinate frequency corresponding to a specific data transmission rate. The apparatus and method provide for data transfer between the interface apparatus (101) and the processor (103) at a second, indeterminate frequency, and provides for interim data storage in memory (115) between data transmission (or data reception) and data processing, such as modulation and demodulation, by the computer processor (103). The apparatus and method further provide for generating an interrupt signal to the processor to indicate the presence of received data for processing and the absence of digital data for transmission.

Abstract: The CPU is one of the major power consumers in a portable computer, and considerable power can be saved by turning off the CPU when it is not doing useful work. In Apple’s MacOS, however, idle time is often converted to busy waiting, and generally it is very hard to tell when no useful computation is occurring. In this paper, we suggest several heuristic techniques for identifying this condition, and for temporarily putting the CPU in a low-power state. These techniques include turning off the processor when all processes are blocked, turning off the processor when processes appear to be busy waiting, and extending real time process sleep periods. We use trace-driven simulation, using processor run interval traces, to evaluate the potential energy savings and performance impact. We find that these techniques save considerable amounts of processor energy (as much as 66%), while having very little performance impact (less than 2% increase in run time). Implementing the proposed strategies should increase battery lifetime by approximately 20% relative to Apple’s current CPU power management strategy, since the CPU and associated logic are responsible for about 32% of power use; similar techniques should be applicable to operating systems with similar behavior.

Abstract: The paper kind sensor 18 discriminates a kind of a paper to be printed by the print section 20. Receiving the paper kind information from the sensor 18, the CPU 10 selects a color-conversion table Ti out of the plurality of color-conversion tables stored in the ROM 8. The selected color-conversion table Ti corresponds to the kind of the presently-used paper. The CPU 10 then performs a color-conversion operation on print data with using the selected color-conversion table Ti. Thus color-converted print data is used in printing operation. A user will not need to consider a kind of paper to be printed, and therefore will not need to control the host computer to correct for print information before supplying the print information to the printer. It becomes possible to reduce a burden loaded on the user.

Abstract: A data processor (3) executes a real time trace function which allows an external development system (7) to dynamically observe internal operations of data processor (3) without assuming a type or availability of an external bus and without significantly impacting the efficiency and speed of the data processor (3). A debug module (10) of data processor (3) provides a parallel output port for providing internal operating information via a DDATA signal and a PST signal. The DDATA signal provides data which reflects operand values and the PST signal provides encoded status information which reflects an execution status of a central processing unit 92). Furthermore, the DDATA signal also provides captured instruction address program flow changes to allow external development system (7) to trace an exact program flow without requiring an externally visible address bus or an externally visible data bus.