Abstract: An electronic form processing system preferably includes a host computer, a plurality of local computers, form definitions, routing definitions and an organizational hierarchy. Both the host and the local computers further include a central processing unit, a display device, an input device and addressable memory. The processing unit accesses information and instructions from the input device and memory to display forms, complete forms and route the completed forms within the hierarchy of users. With the display and input devices, the user inputs the necessary information to select and complete a form. The system creates a data file and electronically sends the data file to the proper recipients based on the form type and routing definition. The system also tracks the data file to assure that the initiator of the form receives a response.

Abstract: The PC based ultrasound system (100) utilizes a standard PC central processing unit (1112), a memory storage (1118) and retrieval components, a scan conversion board (1116) and a video processing board (1114), all electrically linked to the bus (1102) in the computer. The analog drive and return scan video signals are sent to and received from a video processing and motor control unit (1120) which are coupled to an ultrasound scan lead (1122). The virtual control user interface for the ultrasound system includes a software driven display obtained from memory. The software driven display reveals images representative of hardware control configurations for many different ultrasound processors. The virtual control user interface is used in conjunction with a touch sensitive user input screen and the virtual control user interface includes a touch screen input command converter for converting the tactile input into software commands. Other features include the ability to recall previously scanned ultrasound images, and display a checklist for medical protocol.

Abstract: A data processor (20) includes a diagnostic circuit (23) with a first-in, first-out memory (FIFO) (25) for storing sequential states of an internal bus, such as a program address bus. In one mode, the diagnostic circuit (23) halts a central processing unit (CPU) (21) and the FIFO (25) on the occurrence of an event condition, such as a hardware breakpoint. In a second mode, the diagnostic circuit (23) halts the FIFO (25) but keeps the CPU (21) in normal operation. Thus, the contents of the FIFO (25) may be examined through a serial port while the CPU (21) is executing instructions normally.

Abstract: A videographics/video game fabricating system includes a multiprocessor based game processor console which includes a main central processing unit (CPU) which controls editing operations and operating system task execution and a game CPU for executing the model video game which is loaded into a pluggable RAM cartridge. The model video game provides a starting point from which a user can readily create an original video game including desired aspects of the model software. The system includes security features to prevent unauthorized use and copying of proprietary data and program software files. The security features include a unique ID card for insertion into the system console having stored ID DATA corresponding to matching ID DATA associated with certain files stored on floppy disks. In addition, the ID card and a game cartridge may include customized security circuits that authenticate one another.

Abstract: A vehicle control unit comprises an interface software memory for storing an interface software program for connecting an application software program with an operating system in an internal ROM, a central processing unit for performing computation of the application software program and the interface software program, an erasable memory for storing data such as the result of computation, an I/O unit for extending the control unit, and extending means for communicating memory data through a bus or a LAN. A single-chip micro-computer is used in vehicle control.

Abstract: A behavior analyzing antivirus program detects viral infection of a target program by emulating the execution of the target program and analyzing the emulated execution to detect viral behavior. The antivirus monitor program contains both variables corresponding to the CPU's registers and emulation procedures corresponding to the CPU's instructions. The target program is loaded into memory and its execution is emulated by the antivirus monitor program. Intelligent procedures contained in the monitor program are given control between every instruction emulated so as to detect aberrant or dangerous behavior in the target program in which case the danger of a viral presence is flagged and emulation is terminated.

Abstract: An arbitration mechanism is provided for use in a computer system which comprises (i) a central processing unit (CPU); (ii) a first system bus which connects the CPU to system memory so that the CPU can read data from, and write data to, the system memory; (iii) a second system bus connected to the CPU; (iv) a host bridge connecting the second system bus to a peripheral bus, the peripheral bus having at least one peripheral device attached thereto; and (v) an input/output (I/O) bridge connecting the peripheral bus to a standard I/O bus, the standard I/O bus having a plurality of standard I/O devices attached thereto. The arbitration mechanism comprises (i) a first level of logic for arbitrating between the plurality of standard I/O devices, wherein one standard I/O device is selected from a plurality of the standard I/O devices competing for access to the standard I/O bus, and (ii) a second level of logic for arbitrating between the selected standard I/O device, the CPU and the at least one peripheral device, wherein one of the selected standard I/O device, the CPU and the at least one peripheral device is selected to access the peripheral bus. The arbitration mechanism includes sideband signals which connect the first and second levels of arbitration logic and include arbitration identification information corresponding to the selected standard I/O device.

Abstract: A central processing unit (CPU) with facilities for debug support. The debug support facilities include debug support unit (DSU), a debug support interface bus, and a diagnostic instrument. During an execution trace, the DSU transmits trace data such as an instruction address and a trace status via the bus to the diagnostic instrument. Instruction addresses are sent in 4-bit segments in one clock cycle during a trace. Trace status includes an indication of non-sequential instruction execution by the Instruction Unit (IU). A control bit is used to toggle a hold on IU operation where a non-sequential instruction is encountered in trace mode. The diagnostic instrument uses trace data provided by the DSU to generate a complete execution trace in real-time. During breakpoint operations, input such as a debug instruction is provided by the diagnostic instrument via the debug support interface bus to the CPU for execution thereby.

Abstract: A method of using the DAT mechanism in a computer processor to extend both: 1) the native storage access authorization architecture of the processor, and 2) to enable the processor to execute programs designed to operate under different storage access architectures. An executing program (called a source program) uses "source effective addresses" (source EAs) for locating its instructions and storage operands while executing on the processor (called the target processor).

Abstract: A direct memory access (DMA) support mechanism is provided for use in a computer system which comprises (i) a central processing unit (CPU) connected to system memory by a first system bus, and a second system bus connected to the CPU; (ii) a host bridge connecting the second system bus to a peripheral bus; (iii) an input/output (I/O) bridge connecting the peripheral bus to a standard I/O bus, the standard I/O bus having a plurality of standard I/O devices attached thereto; and (v) arbitration logic which functions in an arbitration mode for arbitrating between the plurality of standard I/O devices competing for access to the standard I/O bus, and in a grant mode wherein a selected standard I/O device is granted access to the standard I/O bus. The DMA support mechanism comprises a direct memory access (DMA) controller for performing DMA cycles on behalf of the selected standard I/O device, and direct memory access (DMA) support logic for enabling the DMA cycles to be performed over the peripheral bus. The DMA support logic includes sideband signals directly connecting the DMA controller with the I/O bridge, the sideband signals including information identifying the bus size of the selected I/O device for which the DMA controller is performing the DMA cycles.

Abstract: A hand held data collector and analyzer achieves superior stability, accuracy and reliability through the use of a fixed frequency anti-aliasing filter and two analog to digital converters, one for high frequency signals and one for low frequency signals. Efficient digital filtering and decimation is achieved by providing specialized hardware filters and decimators and implementing software filters and decimators in a data processor. A true zoom method is employed to take advantage of the filtering and decimation capabilities, and independent digital signal processors operate serially on incoming signals to further reduce demands on the central processing unit. In addition, the RAM system memory is formatted as a pseudo-card to facilitate use of a PCMCIA memory card or the RAM system memory.

Abstract: A data stream processing unit comprises a CPU which comprises an ALU, a shift/extract unit, timers, a scheduler, an event system, a plurality of sets of general purpose registers, a plurality of sets of special purpose registers, masquerade registers, pipeline controller, a memory controller and a pair of internal buses. The multiple sets of general and special purpose registers improves the speed of the CPU in switching between environments. The pipeline controller, the scheduler, the events system, and the masquerade registers facilitate the implementation and execution of the methods of the present invention such as efficient thread scheduling, branch delays, elimination of delay slots after stores that provide further increases in the performance and bandwidth.

Abstract: A dual-instruction set central processing unit (CPU) is capable of executing instructions from a reduced instruction set computer (RISC) instruction set and from a complex instruction set computer (CISC) instruction set. Data and address information may be transferred from a CISC program to a RISC program running on the CPU by using shared registers. The architecturally-defined registers in the CISC instruction set are merged or folded into some of the architecturally-defined registers in the RISC architecture so that these merged registers are shared by the two instructions sets. In particular, the flags or condition code registers defined by each architecture are merged together so that CISC instructions and RISC instructions will implicitly update the same merged flags register when performing computational instructions. The RISC and CISC registers are folded together so that the CISC flags are at one end of the register while the frequently used RISC flags are at the other end, but the RISC instructions can read or write any bit in the merged register. The CISC code segment base address is stored in the RISC branch count register, while the CISC floating point instruction address is stored in the RISC branch link register. The general-purpose registers (GPR's) are also merged together, allowing a CISC program to pass data to a RISC program merely by writing one of its GPR's, switching control to the RISC program, and the RISC program reading one of its GPR's that is merged with and corresponds to the CISC GPR that was written to by the CISC program.

Abstract: A computer system has a central processing unit and a functional memory coupled to the central processing unit's memory access circuitry The functional memory includes random access memory circuitry connected in parallel with field programmable gate array circuitry The field programmable gate array circuitry receives configuration data from the central processing unit The configuration data defines what memory addresses the field programmable gate array circuitry will be responsive to and what computational functions the field programmable gate array circuitry will perform The field programmable gate array circuitry includes input registers for storing data received from the central processing unit when the central processing unit's memory access circuitry asserts a first set of memory addresses defined by the configuration data and result output circuitry for communicating the results computed by the field programmable gate array circuitry The result output circuitry outputs result data to the central processing unit when the central processing unit's memory access circuitry asserts a second set of memory addresses defined by the configuration data The functional memory includes access circuitry for routing data signals from the central processing unit to both the random access memory circuitry and the field programmable gate array circuitry in parallel, and for routing data signals from both the random access memory circuitry and the field programmable gate array circuitry to the central processing unit The field programmable gate array circuitry can be reprogrammed to support different computations for different programs

Abstract: In a disk array system, data read out and data written anew are temporarily held as former data in a former data holding portion. When a write operation has occurred, a CPU searches the holding portion for write data, it generates update data from the new and former write data items, and it holds the generated update data in an update data holding portion. In addition, the CPU stores the storage address of redundant data associated with the held update data, as log data in a log data holding portion. Further, the CPU operates asynchronously with the write operation to read out the redundant data of the address of the holding portion, to calculate new redundant data from the read redundant data and the held update data, and to write the new redundant data into the address of the log data. On this occasion, a parity area and a data area are separated so as to heighten read/write processing speeds and a parity generation processing speed.

Abstract: Circuitry and logic are provided to a bus control module of a system bus of a computer system to inject the bus control module into, and win a system test master arbitration process initiated by a live inserted and successfully self tested CPU or I/O board. However, upon winning the system test master arbitration, the bus control module will inform the live inserted CPU or I/O board that it is not interested in having the CPU or I/O board in participating in system wide testing. In fact, the bus control module will not even initiate any system wide testing. As a result, CPU or I/O boards equipped with circuitry and logic to support certain required power on/reset testing protocol may be live inserted into the system without modifications, and without interruption to system operation.

Abstract: There is provided a Direct Access Memory Unit (DAu) that is associated with a remote processor module in a multi-processing system. The DAU performs Direct Memory Access (DMA) operations independently of a Central Processing Unit (CPU) in the remote processor module. The CPU requests a DMA by writing information relevant to the DMA to the remote processor's memory. The address of each control block is written to a circular queue, also in the remote processor's memory. The DAU determines if there are any control blocks to process and if so, the DAU will perform the DMA operation (reading data from or writing data to the memory of the host processor), all without the intervention of the CPU of the remote processor module. The CPU adds a new control block by loading its address in a location in the circular queue that is ahead of the circular queue location that the DAU is processing. The CPU can abort a pending DMA request during DAU operations by setting a skip bit in the control block. Upon the completion of performing a DMA request, the DAU will set a complete bit in the control block in the remote processor's memory. An interrupt can also be sent to the CPU, wherein the CPU is advised that a DMA request has been completed. The data in a DMA operation is sent in bursts to a buffer located between two busses having different data transmission rates.

Abstract: A microcomputer mounted on a single semiconductor chip includes a central processing unit and a nonvolatile flash memory which allows the information to be processed by the central processing unit to be re-programmed by electrical erasing and programming operations. The microcomputer is provided with a normal power supply voltage terminal and a programming power supply voltage terminal and also incorporates a power supply voltage level detection device and an internal voltage boost circuit to decide the re-programming mode for the flash memory according to the level of the voltage supplied and to select between the boost voltage and the external high voltage in performing the erasing and programming of data.

Abstract: A computer system having a CPU, a power management processor, a switch, a modem, a timer, an override circuit, a glitch circuit, and a power supply in circuit communication. The power supply has several power supply states, which are controlled by the power management processor responsive to the CPU, the switch, the modem, the timer, the glitch circuit, the override circuit, and the power management processor itself.

Abstract: A structure and a format provide a video signal encoder under the MPEG (Motion Picture Experts Group) standard In one embodiment, the video signal interface is provided with a decimator for providing input filtering for the incoming signals In one embodiment, the central processing unit (CPU) and multiple coprocessors implements discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) and other signal processing functions, generating variable length codes, and provides motion estimation and memory management The instruction set of the central processing unit provides numerous features in support for such features as alpha filtering, eliminating redundancies in video signals derived from motion pictures and scene analysis In one embodiment, a matcher evaluates 16 absolute differences to evaluate a "patch" of eight motion vectors at a time

Abstract: A videographics/video game fabricating system includes a multiprocessor based game processor console which includes a main central processing unit (CPU) which controls editing operations and operating system task execution and a game CPU for executing the model video game which is loaded into a pluggable RAM cartridge. The model video game provides a starting point from which a user can readily create an original video game including desired aspects of the model software. The system permits a user to modify any of the game's moving objects, background screens, music or sound effects. The main CPU and game CPU cooperate in the game execution and editorial process such that an editing screen generated by the main CPU is superimposed on a game screen generated by the program executing CPU. The system utilizes unique "unit" based data structures in which moving objects are processed on a unit basis and where each object is assigned a unit ID which is associated with a wide range of object, game characteristics, game processing and location data including status information, present screen display location, object format, character size, pose information, collision threshold information, tempo information, attribute data, and animation data. A wide range of information is likewise stored in data structures associated with background screens referred to as "stage" data.

Abstract: An apparatus and method for scheduling a sequence of instructions for achieving multiple launches and multiple executions of the instructions within a central processing unit. Each of the instructions is classified according to which one of multiple execution resources of the central processing unit executes the instruction. The classifications include memory reference operations, integer operations, program control operations, and floating point arithmetic operations. The classifications associated with the instructions occur in the order in which the instructions occur in the sequence.

Abstract: A single-instruction, multiple-data (SIMD) execution unit for use in conjunction with a superscalar data processing system is provided. The SIMD execution unit is coupled to a branch execution unit within a superscalar processor. The branch execution unit fetches instructions from memory and dispatches vector processing instructions to the SIMD execution unit via the instruction bus. The SIMD execution unit includes a control unit and a plurality of processing elements for performing arithmetic operations. The processing elements further include a register file having multiple registers and an arithmetic logic unit coupled to the register file. The arithmetic logic unit may include a fixed-point unit for performing fixed-point vector calculations and a floating-point unit for performing floating-point vector calculations. Once the control unit within the SIMD execution unit receives a vector instruction, the control unit translates the instruction into commands for execution by selected processing elements within the SIMD execution unit. If such a vector instruction requires access to memory, a fixed point execution unit within the superscalar processor may be utilized to calculate a memory address which is then utilized by the SIMD execution unit to access memory.

Abstract: An image processing apparatus coupling at least two image processing systems connected to a network. The network couples image information to each system, and each system displays at least one image. Each system includes a communication unit and a control unit. The communication unit couples information to and receives information from the network. The control unit includes a central processing unit (CPU) and a partitioned memory space, including, both common and personal memory. The personal memory of each system contains one or more personal images that can be viewed only by the respective system, wherein each system is controlled to access only its respective personal memory. Under control of the CPUs in the respective systems, a common image is coupled to each system over the network and commonly displayed on each system. While the common image is commonly displayed on each system, it is edited by the first image processing system.

Abstract: An improved instruction tracing mechanism provides a combination of hardware, internal to the CPU, and novel software. Additional registers are added to interconnected to the CPU. These registers store values indicating the instruction address, data address, whether the instruction was a load or store, the number of bytes moved and whether any address mapping changes occurred. The registers are read by a trace interrupt handler which then provides the information to a trace buffer and a profile buffer. The end user can then access the trace and profile information through the input/output (I/O) system of the data processing system.

Abstract: In a pipelined processor, an instruction queue and an instruction control unit is provided to group and issue m instructions simultaneously per clock cycle for execution. An integer and a floating point function unit capable of generating n 1 and n 2 integer and floating point results per clock cycle respectively, where n 1 and n 2 are sufficiently large to support m instructions being issued per clock cycle, is also provided to complement the instruction queue and instruction control unit. The pipeline stages are divided into integer and floating point pipeline stages where the early floating point stages overlap with the later integer pipeline stages. The instruction queue stores sequential instructions of a program and target instructions of a branch instruction of the program, fetched from the instruction cache. The instruction control unit decodes the instructions, detects operands cascading from instruction to instruction, group instructions into instruction groups of at most m instructions applying a number of exclusion rules, and issuing the grouped instructions simultaneously to the integer and/or floating point unit for execution. The exclusion rules reflect the resource characteristics and the particular implementation of the pipelined processor. The instruction control unit also tracks the history of the instruction groups and uses the history in conjunction with the exclusion rules in forming the instruction groups.

Abstract: A system for distributing power throughout a computer system, preferably a portable computer, while still maintaining a desired power mode hierarchy so that the most critical components or circuits-within the computer system receive power before non-critical components. The system includes a micro-controller unit for controlling power allocations throughout the system. The system further includes a power connector for interfacing with a dual-line AC-to-DC adapter, a switching regulator for providing regulated DC power outputs to a central processing unit, memory unit and the like, a battery switching circuit having two battery packs to support simultaneous charging and sequential discharging of the battery packs in the event that the AC-to-DC adapter is decoupled from the computer system and an auxiliary battery source for supplying power to critical components in the computer system as a last resort.

Abstract: A central processing unit (CPU) is coupled to a display device, an input device, a data storage device and a memory with charting and diagramming tools, element records, connector records, and display routines. The memory is used by the CPU to present a user interface on the display and for generating chart elements in response to inputs from the user. The CPU displays a user interface that allows automatic generation and connection of new drawing elements. Methods are disclosed for creating drawing elements of a flowchart, creating drawing elements of a flowchart at a selected position, creating drawing elements of an organizational chart, and displaying a portion of the display in a visually distinct manner.

Abstract: The CPU-controlled garbage-collecting memory module (CPU-C GCMM) is essentially an intelligent memory that connects to a central processing unit (CPU) and performs the routine and repetitive tasks associated with a spectrum of garbage-collecting techniques under the direction and control of the CPU. The CPU-C GCMM performs its garbage-collecting tasks as background tasks to be performed when the CPU-C GCMM is not burdened with the ordinary fetch and store operations necessitated by the application programs being run on the CPU. The CPU-C GCMM can be structured in a variety of ways. One species which embodies the essence of the invention includes a memory and a memory controller which provides the means for reading data from and writing data to the memory. The memory controller receives fetch requests directly from the CPU and returns the requested data immediately even though the data may be incorrect in certain instances. A microcontroller which exercises overall control over the component parts of the CPU-C GCMM together with a fetch monitor work together to repair any incorrect data deliveries to the CPU by the memory controller. A communication-channels unit provides the means of communication between the CPU and the microcontroller for handling all interactions between the CPU and the CPU-C GCMM except fetch requests. An object space manager unit provides a means for rapidly identifying the header of an object given a pointer to the interior of an object.