Showing papers on "Central processing unit published in 1992"
Patent•
[...]
TL;DR: In this paper, a non-contact IC card includes a data transmitting/receiving device, a memory, a CPU, a first determining device, and a second determining device.
Abstract: A non-contact IC card include a data transmitting/receiving device, a memory, a CPU, a first determining device, a second determining device, and a stopping device. When the data transmitting/receiving device receives a request signal, the first determining device determines whether first system identification information stored in the memory agrees with second system identification information contained in the request signal. At the same time, the second determining device determines whether use of the IC card indicated by use authorization information stored in the memory is authorized. When the first and second system identification information do not agree or when the use authorization information indicates that use of the IC card is not authorized, the stopping device stops the operation of the CPU until the next request signal is received.
259 citations
TL;DR: Motorola's second-generation RISC microprocessor, which uses advanced techniques for exploiting instruction-level parallelism, including superscalar instruction issue, the authors'-of-order instruction completion, speculative execution, dynamic instruction rescheduling, and two parallel, high-bandwidth, on-chip caches, is discussed.
Abstract: Motorola's second-generation RISC microprocessor, which uses advanced techniques for exploiting instruction-level parallelism, including superscalar instruction issue, our-of-order instruction completion, speculative execution, dynamic instruction rescheduling, and two parallel, high-bandwidth, on-chip caches, is discussed. The microprocessor was designed to serve as the central processor in low-cost personal computers and workstations, and support demanding graphics and digital signal processing applications. The 88110's instruction set architecture, instruction sequencer, register files, execution units, address translation facilities, caches, and external bus interface are described. >
207 citations
Patent•
15 Jul 1992
TL;DR: In this article, a telecommunications system is provided to connect a plurality of dissimilar types of subscriber telecommunications devices and to provide integrated telecommunications services, where a digital communications link comprising a PCM bus for voice and data and an HDLC coded PCM highway for control signals to create a master slave environment.
Abstract: A telecommunications system is provided to connect a plurality of dissimilar types of subscriber telecommunications devices and to provide integrated telecommunications services. The system is provided with a digital communications link comprising a PCM bus for voice and data and an HDLC coded PCM highway for control signals to create a master slave environment, wherein a central processing board operates as a master processor for a plurality of peripheral processor boards. The peripheral boards are coupled to various subscriber telecommunications devices. The CPU board is provided with hierarchical program control that includes low level program code for driving CPU board components, and mid-level program code for effecting system functions and CPU board functions. The mid-level code can also be used to create data bases relating to system configuration as well as data bases for each port associated with the peripheral boards. The mid-level code is also provided with an interpreter program code for executing a novel high level code to program code that is recognized by the master CPU board. The high level, telecommunications language provides a system user with a programming language to create program modules for processing packets of data. The hierarchical program control levels operate to conceal dissimilarities between the subscriber telecommunications units to facilitate use of the high level programming language.
145 citations
Patent•
31 Mar 1992TL;DR: In this article, a system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions is presented.
Abstract: A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a portion of the stream of complex instructions and extracts a first set of instruction bytes starting with the first instruction bytes, using an extract shifter. The set of instruction bytes are then passed to an align latch where they are aligned and output to a next instruction detector. The next instruction detector determines the end of the first instruction based on said set of instruction bytes. An extract shifter is used to extract and provide the next set of instruction bytes to an align shifter which aligns and outputs the next instruction. The process is then repeated for the remaining instruction bytes in the stream of complex instructions. The isolated complex instructions are decoded into nano-instructions which are processed by a RISC processor core.
127 citations
Patent•
7 Sep 1992
TL;DR: In this paper, a switching network coupled between the data storage array systems and the multiple processors is proposed to provide the ability for any CPU to be directly coupled to any storage array.
Abstract: A multiprocessing computer system with data storage array systems allowing for linear and orthogonal expansion of data storage capacity and bandwidth by means of a switching network coupled between the data storage array systems and the multiple processors. The switching network provides the ability for any CPU to be directly coupled to any data storage array. By using the switching network to couple multiple CPU's to multiple data storage array systems, the computer system can be configured to optimally match the I/O bandwidth of the data storage array systems to the I/O performance of the CPU's.
112 citations
Patent•
18 Aug 1992TL;DR: In this article, a power supply control system for a portable computer having a central processing unit (CPU), and operable in response to power supplied from a rechargeable battery or an alternating current (AC) adapter is presented.
Abstract: A power supply control system for a portable computer having a central processing unit (CPU), and operable in response to power supplied from a rechargeable battery or an alternating current (AC) adapter. The control system includes a charge unit for charging the rechargeable battery; current detectors for detecting power status; and a power control microprocessor for controlling the charge unit independently of the CPU in response to a detected power status.
96 citations
Patent•
9 Oct 1992TL;DR: In this paper, the address translation circuit inverts a predetermined bit of each address output by the CPU, thereby allowing access to the boot block storing a far jump instruction, which is used to refresh the contents of the BIOS-ROM.
Abstract: A personal computer uses a flash memory equipped with a main block storing a boot block and a basic input/output system as its BIOS-ROM. An address translation circuit, after power-on reset, supplies addresses output by a central processing unit to the BIOS-ROM as they are to thereby allow access to the boot block storing a far jump instruction. After system startup, the address translation circuit inverts a predetermined bit of each address output by the CPU to thereby allowing access to the BIOS. To refresh the contents of the BIOS-ROM, the CPU transfers a BIOS stored on a floppy disk to the main block of the BIOS-ROM.
84 citations
Patent•
16 Apr 1992TL;DR: In this paper, a system for proactively automating the use of a computer comprises a central processing unit (CPU), an input device, a display device and memory including a set of feature templates, context monitoring unit, input monitoring units, feature presentation routines and feature implementation routines.
Abstract: A system for proactively automating the use of a computer comprises a central processing unit (CPU), an input device, a display device and memory including a set of feature templates, context monitoring unit, input monitoring unit, feature presentation routines and feature implementation routines. The CPU is coupled to the display device and input devices for displaying information and receiving information, respectively. The CPU is also coupled to the input monitoring unit and the context monitoring unit to detect and record user manipulations of the input device and its context. The CPU is also coupled to a section of memory containing feature templates. Each template is a set of input manipulation steps and program contexts. The CPU compares the recorded user manipulations of the input and their corresponding program context with the feature templates stored in memory. If a match is found, the CPU uses the feature presentation routines to present different features on the display to the user and implements the features with the feature implementation routines according to user selection.
82 citations
Patent•
16 Jan 1992
TL;DR: In this paper, a television game console has a central processing unit and an electronic control device for controlling the allowable playing time of the TV game console, which includes a timer control device which interfaces with a game cartridge read only memory unit.
Abstract: A television game console has a central processing unit and an electronic control device for controlling the allowable playing time of the television game console. The electronic control device includes a timer control device which interfaces the central processing unit with a game cartridge read only memory unit. The timer control device has a current time clock output and receives a presettable allowable playing time range input from the central processing unit. The timer control device electrically connects the game cartridge read only memory unit and the central processing unit only when the current time clock output is within the allowable playing time range.
82 citations
Patent•
13 Oct 1992
TL;DR: In this paper, a data processing apparatus and method are described in which a CPU is operable in either a main processing (User32) or an exception processing mode (e.g. FIQ32).
Abstract: A data processing apparatus and method are described in which a CPU is operable in either a main processing mode (User32) or an exception processing mode (e.g. FIQ32). The CPU has a plurality of main data registers (R0 to R15) and a processing status register (CPSR) for use in the main processing mode. Upon entering the exception processing mode at least one exception data register (R8fiq to R14fiq) is substituted for use in place of a respective corresponding one of the main data registers and the data held within the processing status register is stored within a saved processing status register (SPSRfiq). When the exception processing mode is left, the main data registers are returned for use in place of the exception data registers and the data stored within the saved processing status register is restored to the processing status register. A plurality of exception processing modes are described each having their own associated exception data registers. When a further differing exception occurs within an exception processing mode, the CPU switches to that further differing exception processing mode and uses its own exception data registers and saved processing status register in place of those of the existing processing mode. In this way, nested exception processing is provided.
81 citations
Patent•
5 Jun 1992TL;DR: In this article, a metal frame is fabricated from magnesium alloy and all the main components of the computer, including the logic board, the hard disk drive, the keyboard, upper and lower halves of computer's case, and the pivoting display screen are all directly attached to the frame.
Abstract: A metal frame is fabricated from magnesium alloy and all the main components of the computer, including the logic board, the hard disk drive, the keyboard, the upper and lower halves of the computer's case, and the pivoting display screen are all directly attached to the frame. The frame thus offers a method for constructing a personal computer which will have greatly improved shock resistance, integrated electromagnetic isolation, and structural strength, without increasing the weight of the completed computer in any significant fashion. Additionally, by means of a cooling flange fabricated as part of the frame, the central processing unit of the portable computer is thermally connected to the frame, which then acts as a heat-sink for the central processing unit, greatly improving its reliability.
Patent•
31 Aug 1992TL;DR: An improved hardware modeling system that is preferably embodied as a stand-alone system for networked connection to one or a variety of host computers that are used to design digital electronics systems is described in this paper.
Abstract: An improved hardware modeling system that is preferably embodied as a stand-alone system for networked connection to one or a variety of host computers that are used to design digital electronics systems, the hardware modeling system having a network interface for communicating between the hardware modeling system and the host computer, a central processing unit for controlling operation of the hardware modeling system, a central timing unit for generating timing signals for use in the operation of the hardware modeling system including the generation of precision clocks, data formatting strobes and sample strobes, an internal pattern bus for transmission of read/write requests from the central processing unit in one operational mode and pattern sequences for stimulation of the hardware modeling element in a second operational mode, a pattern controller for controlling presentation and delivery of the pattern sequences to the pattern bus, a pattern memory connected to the pattern controller for storing stimulus pattern sequences, pin electronics circuitry which is used for driving the pattern sequences on the pattern bus to the hardware modeling element and then sensing the five state values of the hardware modeling element pins, and an adapter that is used for fixturing the hardware modeling element to the pin electronics circuitry with the adapter supporting live insertion into a powered hardware modeling system.
Patent•
21 Oct 1992TL;DR: In this paper, a microprocessor system is implemented with a transfer signal control line, and second data bus lines interconnecting the data source and data destination devices for direct background transfer of data between the devices.
Abstract: A microprocessor system, including a central processing unit (CPU), data source device and data destination device electrically interconnected by first data bus lines, address bus lines and control bus lines of a system bus, is implemented with a transfer signal control line, and second data bus lines interconnecting the data source and data destination devices for direct background transfer of data between the devices. At least one of the devices includes individually sequentially addressable storage locations, and associated address and count registers. The data source device includes "ready" and "enable output" terminals, and the data destination device includes "ready" and "enable input" terminals, all connected in AND-gate configuration so that the devices are enabled for data transfer through the second data bus lines only when both device "ready" signals and the transfer control signal are all present. A starting address is loaded in the address register and a total data unit count is loaded in the count register using the first data bus lines. The transfer control signal is then given, with the address and count registers incremented after each data unit is transferred. Once the process is started, data is transferred data unit-by-data unit and without the need for direct CPU involvement, in synchronism with the system clock, until the count register indicates completion of transfer of the entire block.
TL;DR: The R4000's superpipelining techniques allow it to process more instructions simultaneously than the previous generation of microprocessors, and it is shown that, according to SPEC benchmark tests, it achieves the highest performance of any microprocessor chip.
Abstract: The R4000, a highly integrated, 64-b RISC microprocessor that provides a simple solution to the increasing demands on the size of address space while maintaining full compatibility with previous Mips processors, is described. The microprocessor's on-chip central processing unit, floating point unit, memory management unit, primary caches, system interface logic, secondary cache control logic with flexible interface, the programmable system interface for high-performance multiprocessor servers and low-cost desktop systems, the flexible multiprocessor support, and the 1.2 million transistors implemented in CMOS technology are discussed. The R4000's superpipelining techniques allow it to process more instructions simultaneously than the previous generation of microprocessors. It is shown that, according to SPEC benchmark tests, it achieves the highest performance of any microprocessor chip. >
Patent•
19 Feb 1992TL;DR: In this article, a RAM row refresh signal is generated to only a selected number of rows of memory cells within the random access memory stage, after a central processing unit has read a given software program to determine its data storage requirements.
Abstract: A system and method for minimizing power consumption in personal computers and for controlling the power requirements of a random access memory based upon the actual RAM requirements of given software application. Using this method and system, a predetermined number of rows of RAM storage capacity may be refreshed at any given time and at a controlled refresh frequency after a central processing unit has read a given software program to determine its data storage requirements. A novel RAM control system is connected between the output of the central processing unit and one or more inputs to the RAM storage stage and is operative in a novel manner to generate RAM row refresh signals to only a selected number of rows of memory cells within the random access memory stage.
Patent•
22 Oct 1992TL;DR: In this article, a high speed data communication controller comprising two independent central processing units, each having its own independent program instruction fetch data path and instruction execution data path, is presented, which includes a dual-port serial communication subsystem and a bus interface unit associated with a four channel DMA controller.
Abstract: A high speed data communication controller comprising two independent central processing units, each having its own independent program instruction fetch data path, and instruction execution data path. The data communication controller includes a dual-port serial communication subsystem and a bus interface unit operably associated with a four channel DMA controller. One central processing unit is assigned the task of handling the medium access control (MAC) layer function of a multilayered local area network protocol, while the other central processing unit handles host commands and buffer memory management functions associated with the transmission and reception of packets relating to the higher layer protocol. As a result of the present invention, efficient data communication processing is achieved within a single VSLI chip, thereby improving node and network data throughout.
Patent•
16 Apr 1992
TL;DR: In this article, the first and second shells define trays of disparate depths and rear walls of similar height and hingedly connected together, with side and front walls defining a minimal height generally not exceeding the height of a CPU/keyboard unit closely confined within the first shell tray.
Abstract: A protective housing for portable computers includes first and second shells defining trays of disparate depths and rear walls of similar height and hingedly connected together. With side and front walls of the first shell defining a minimal height generally not exceeding the height of a CPU/keyboard unit closely confined within the first shell tray, a user has un-impeded access to the keyboard while opening(s) in one or more walls of the first shell overlie access to various drives and/or ports adapted to communicate with external peripheral devices. Higher side and front walls on the second shell define a tray of greater depth and within which is disposed a portable printer having a cable directly communicating with the CPU in the first shell.
Patent•
IBM1
TL;DR: A priority preemptive, time distribution operating system operating in accordance with the method of the present invention provides enhanced efficiency in operation of a data processing system having a central processing unit, a computer memory and an auxiliary memory.
Abstract: A priority preemptive, time distribution operating system operating in accordance with the method of the present invention provides enhanced efficiency in operation of a data processing system having a central processing unit, a computer memory and an auxiliary memory. The operating system manages the central processing unit, the computer memory and the auxiliary memory where a plurality of processes are presented for execution on the central processing unit by: ordering the processes for execution; allocating a predetermined time slice for execution of a process from the ordering; executing a first current process in the ordering on the central processing unit for the predetermined time slice; responsive to occurrence of a storage access operation during execution of the first current process, allocating a supplemental time slice to the current process for execution; and continuing execution of the current process for the supplemental time slice.
Patent•
27 Jan 1992
TL;DR: In this paper, a multi-task control device is used to switch between a plurality of tasks executed by the CPU by using means other than the CPU including such means for controlling operations needed for comparing priority orders between different tasks, and other means for generating interrupt operations from this control device against the CPU needed for switching tasks being executed in accordance with the result of the priority comparative operations.
Abstract: A computer peripheral device incorporating a multi-task control device which is extremely useful for such programs controlling the microcomputer system. In particular, the multi-task control device effectively controls a plurality of tasks executed by the CPU by using means other than the CPU including such means for controlling operations needed for comparing priority orders between a plurality of tasks, and the other means for generating interrupt operations from this control device against the CPU needed for switching tasks being executed in accordance with the result of the priority comparative operations.
Patent•
2 Nov 1992
TL;DR: In this article, a consumer interactive multi-media system is described in which a CPU (102) is loosely coupled with system memory (108), and a graphics manipulation processor (spryte engine) performs substantially all of the graphics rendering and manipulation functions.
Abstract: A consumer interactive multi-media system in which a CPU (102) is loosely coupled with system memory (108), and a graphics manipulation processor (spryte engine) performs substantially all of the graphics rendering and manipulation functions. The spryte system accesses the memory by DMA and has a significantly higher bus priority than does the CPU (102). Graphic images are stored, rendered and manipulated in a compressed format (166), both in terms of the number of bits stored per pixel and in terms of the number of pixels stored per frame. The frame buffer information is read out from a serial port of the system memory and expanded to full 640 by 480 pixel format, with a substantially full 24-bit color resolution, all within the video display path. The resulting images are nearly of broadcast quality and can be made highly realistic. Commands to modify CLUT tables or other parameters in the video display path are provided via the display path itself, and so are automatically synchronized appropriately with pixels, scan lines, fields and frames. The system also includes an audio manipulation processor (162) which receives audio sample data via DMA from the system memory (108), also with a higher priority than the CPU (102).
Patent•
28 Dec 1992
TL;DR: In this article, an upgradeable/downgradeable data processing system capable of operating with different types of central processing units (CPUs) is described, with means for preventing possible signal contention between the first and second CPU, and for synchronizing clocks for operating a CPU with the system clock.
Abstract: An upgradeable/downgradeable data processing system capable of operating with different types of central processing units (CPU). The system has a first socket for registration of a first CPU and a second socket for registration of a second CPU. Means are provided for preventing possible signal contention between the first and second CPU, and for synchronizing clocks for operating a CPU with the system clock. Means are also provided for interfacing with a coprocessor associated with the different types of CPU as well as for adjusting the signals to and from the CPU to the signal width of the system.
Patent•
31 Dec 1992
TL;DR: A portable computer includes a processor, processor associated memory and control circuitry, and a memory disk drive assembly for storing software programs to form an integral computer unit as mentioned in this paper, which is a portable computer that includes a CPU module, a display module, user control module with a user control interface, module connectors, environmental protective barriers for blocking entry of EMI and moisture into the computer unit and a vibration isolator for energy absorbingly mounting the unit to the drive assembly.
Abstract: A portable computer includes a processor, processor associated memory and control circuitry, and a memory disk drive assembly for storing software programs to form an integral computer unit. The integral computer unit has a CPU module, a display module, a user control module with a user control interface, module connectors, environmental protective barriers for blocking entry of EMI and moisture into the computer unit and a vibration isolator for energy absorbingly mounting the unit to the drive assembly. The display module includes a display device that is separately housed and removably interconnected with the CPU module. The modules are connected by hinges along at least one interconnecting edge of each module. The module connectors are disposed along at least one interconnecting edge of each of the modules to permit separation of the modules at non-hinged edges and pivotal movement about the hinged edges for improved accessibility. The connecting hardware may include a protrusion and groove in each module. Preferably, a gasket is included between the protrusion and groove. The computer preferably includes a fan assembly with an air sensor for sensing airflow through the fan assembly.
Patent•
IBM1
TL;DR: In this article, a data processing system is provided for executing multimedia applications which interface with multimedia end devices that consume or produce at least one of (a) real-time and (b) asynchronous streamed data.
Abstract: A data processing system is provided for executing multimedia applications which interface with multimedia end devices that consume or produce at least one of (a) real-time and (b) asynchronous streamed data. The data processing system includes a central processing unit for data processing operations including execution of the multimedia application, a digital signal processor for processing data including the streamed data, and a plurality of modular components which cooperate to provide a substantially open architecture. The plurality of modular components include a plurality of modular multimedia software tasks which are executable by the digital signal processor and which may be called by the multimedia application for execution in the digital signal processor, as well as a plurality of data communication modules for linking selected ones of the plurality of modular multimedia software tasks with selected others of the plurality of modular multimedia software tasks, and for linking selected multimedia end devices with selected ones of the plurality of modular multimedia software tasks. Each of the plurality of data communication modules allows continuous, real-time and unidirectional communication of streamed data. The enhanced connectivity of the modular approach for the multimedia data processing system allows additional modular multimedia software tasks to be added to the plurality of modular multimedia software tasks and selectively linked to selected ones of the plurality of modular multimedia software tasks and selected ones of the multimedia end devices.
Patent•
[...]
17 Jun 1992
TL;DR: In this article, a luminance data Y is fetched to a line memory 40 via a printer controller 26 and compared with an exposure-over threshold level TH and when the level of the data Y was the level TH or over, '1' was written to a RAM area of a CPU 36 (part of RAM 38).
Abstract: PURPOSE:To obtain an excellent print picture even from any picture by preparing several kinds of gradation conversion curves, discriminating automatically an input picture in the case of selecting a curve in response to the state of the input picture so as to select a curve automatically CONSTITUTION:A luminance data Y is fetched to a line memory 40 via a printer controller 26 and compared with an exposure-over threshold level TH and when the level of the data Y is the level TH or over, '1'is written to a RAM area of a CPU 36 (part of RAM 38) Then the level is compared with a flash pickup threshold level TL(TL
Patent•
10 Feb 1992TL;DR: In this article, a cache memory and a data processor including the cache memory, for processing at least one variable length instruction from a memory and outputting processed information to a control unit, such as a central processing unit (CPU).
Abstract: A cache memory, and a data processor including the cache memory, for processing at least one variable length instruction from a memory and outputting processed information to a control unit, such as a central processing unit (CPU). The cache memory includes a unit for decoding an instruction length of a variable length instruction from the memory, and a unit for storing the variable length instruction from the memory, together with the decoded instruction length information. The variable length instruction and the instruction length information thereof are fed to the control unit. Accordingly, the cache memory enables the control unit to simultaneously decode a plurality of variable length instructions and thus realize high speed processing.
Patent•
NEC1
TL;DR: In this article, a microcomputer comprises a central processing unit, a watchdog timer, and an interrupt controller processing as a non-maskable interrupt the watchdog timer processing request generated by the watch timer.
Abstract: A microcomputer comprises a central processing unit, a watchdog timer generating a watchdog timer processing request when an overflow occurs in the watchdog timer, and an interrupt controller processing as a non-maskable interrupt the watchdog timer processing request generated by the watch timer. The central processing unit generates a preset signal to the watchdog timer at a beginning of execution of another interrupt processing by the central processing unit, so as to preset the watchdog timer. The interrupt controller responds to the preset signal for cancelling the watchdog timer processing request generated by the watchdog timer in a period of time of retaining the watchdog timer processing request by the interrupt controller.
Patent•
IBM1
TL;DR: In this article, a vector operation capability is integrated into the execution unit (E-Unit) portion of a computing systems central processing unit (CPU) designed to support scalar instruction processing.
Abstract: A vector operation capability is integrated into the execution unit (E-Unit) portion of a computing systems central processing unit (CPU) designed to support scalar instruction processing. The fixed point and floating point instruction functional units in the E-Unit that are required to implement the vector instruction set are pipelined. A set of vector registers are added to the architected data registers contained in the E-Unit. The E-Unit control logic is modified to queue and schedule both vector and scalar instructions, The E-Unit's load and store unit bandwidth capability to support the transfer of the contiguous blocks of data normally associated with vector processing are enhanced. The integrated vector and scalar capability allows for improved processing of programs that include both vector and scalar type instructions.
Patent•
10 Jan 1992TL;DR: In this paper, the authors propose a comparison method to invalidate data in an internal cache memory of a processor (20-1,20-2,2020-2-2020-3) which differs from that in the external cache memory (220,221).
Abstract: A computer system has a plurality of processing units (2-1,2-2,2-n) connected via one or more system buses (1-1,1-2). Each processing unit (2-1,2-2,2-n) has three or more processors (20-1,20-2,20-3) on a common support board (PL) and controlled by a common clock unit (1000). The three processors (20-1,20-2,20-3) perform the same operation and a fault in a processor (20-1,20- 2,20-3) is detected by comparison of the operations of the three processors (20-1,20-2,20-3). If one processor (20-1,20-2,20-3) fails, the operation can continue in the other two processors (20-1,20-2,20-3) of the processing unit (2-1,2-2,2-n), at least temporarily, before replacement of the entire processing unit (2-1,2- 2,2-n). Furthermore, the processing unit (2-1,2-2,2-n) may have a plurality of clocks (A,B) within the clock unit (1000), with a switching arrangement so that the processors (20-1,20-2,20-n) normally receive clock pulses from a main clock (A), but receive pulses from an auxiliary clock (B) if the main clock (A) fails. Switching between the main and auxiliary clock (A,B) involves comparison of the pulse duration from the clocks (A,B). Additionally, a plurality of cache memories (220,221) may be connected in common to the processors (20-1,20-2,20-3), so that failure of one cache memory (220,221) permits the processing unit (2-1,2-2,2-n) to continue to operate using the other cache memory (220,221). Coherence of the contents of the cache memories (220,221) may be achieved by direct comparison, and a comparison method can also be used to invalidate data in an internal cache memory (2020- 1,2020-2,2020-3) of a processor (20-1,20-2,20-3) which differs from that in the external cache memory (220,221). Coherence of protocols may also ensure that data in caches (220,221) of the different processor units (2-1,2-2,2-n) are always correct.
Patent•
21 Oct 1992TL;DR: A bank-structured processor as discussed by the authors is a processor that includes a central processing unit (CPU) comprising a plurality of data memories serving as general-purpose registers, and a bank specifying registers for use in specifying an address to save and restore data without involving an external system bus which connects the CPU and a program memory.
Abstract: A processor includes a bank-structured memory and is capable of handling multiple interrupts. The processor includes a central processing unit (CPU) comprising a plurality of data memories serving as general-purpose registers, and a plurality of bank specifying registers for use in specifying an address to save and restore data without involving an external system bus which connects the CPU and a program memory, such as a built-in read only memory (ROM), for storing a user program. The processor further includes a bank structured memory, connected to the CPU via an exclusive-use data bus, for holding data stored in the data memories using the bank specifying registers and for returning data stored in the bank structural memory to the data memories using the bank specifying registers. The bank specifying registers include a current bank pointer (CBP) or register for indicating a position of a bank presently in use, and a previous bank pointer (PBP) or register for indicating a bank position of data to be returned to the data memories after completing an interrupt routine. The processor may also include a program counter (PC) for indicating an address of a next instruction to be executed by the processor, a processor status word (PSW) for indicating a status of the processor, and a user stack pointer (USP) for indicating an address of a bank storing values of the program counter.
Patent•
8 Dec 1992TL;DR: A non-contact IC card includes a CPU for processing data, a memory for storing a program for controlling the CPU, an antenna for transmitting data and receiving data manner, a plurality of receivers each having a different signal detection level for detecting a signal received by the antenna, a selector for selecting one of the receivers and connecting it to the CPU and a transmitter for transmitting a signal from the CPU through the antenna.
Abstract: A non-contact IC card includes a CPU for processing data, a memory for storing a program for controlling the CPU, an antenna for transmitting data and receiving data manner, a plurality of receivers each having a different signal detection level for detecting a signal received by the antenna, a selector for selecting one of the plurality of receivers and connecting it to the CPU, and a transmitter for transmitting a signal from the CPU through the antenna.