Abstract: The IBM RISC System/6000 (RS/6000) floating-point unit (FPU) exemplifies a second-generation RISC CPU architecture and an implementation which greatly increases floating-point performance and accuracy. The key feature of the FPU is a unified floating-point multiply-add-fused unit (MAF) which performs the accumulate operation ({ital A} {times} {ital B}) + {ital C} as an indivisible operation. This single functional unit reduces the latency for chained floating-point operations, as well as rounding errors and chip busing. It also reduces the number of adders/normalizers by combining the addition required for fast multiplication with accumulation. The MAF unit is made practical by a unique fast-shifter, which eases the overlap of multiplication and addition, and a leading-zero/one anticipator, which eases overlap of normalization and addition. The accumulate instruction required by this architecture reduces the instruction path length by combining two instructions into one. Additionally, the RS/6000 FPU is tightly coupled to the rest of the CPU, unlike typical floating-point coprocessor chips.

Abstract: The invention is a system for protecting the security of computer files. It has hardware elements, including a programmable auxiliary memory and control unit along with associated software elements. The security subsystem is installed on the host computer bus so that it resides in the control logic, address, and data signal path between the computer storage device and central processing unit. The security system is accessible by the computer operating system only during installation and initialization. Thereafter it is inaccessible to or by the operating system. Supervisor determined criteria for access permission to read, write and execute files are entered into the auxiliary memory system where they are protected from alteration. The security system will deny access to users with invalid entry criteria and refuse to write data to the file storage device when unauthorized operations have been attempted. When breaches of these types occur the security system can lock the computer against further activity until it is released by entry of a master password from supervisory or security personnel. The system maintains a protected area in the computer memory device where, among other data, file signatures of all valid files are retained. The protected area of memory also maintains appropriate signatures of all internal files in the security system so that they can be automatically checked for integrity.

Abstract: The universal remote control system includes a universal remote control comprising an input including a set of keys or push buttons for inputting commands into the remote control, infrared signal output circuitry for supplying an infrared signal to a controlled device including IR lamp driver circuitry, a central processing unit (CPU) coupled to the input and to the signal output circuitry, a single, non-volatile read-write memory coupled to the CPU and data coupling circuitry including terminal structure comprising a receiving port coupled to the CPU for enabling code data for creating appropriate IR lamp driver instructions for causing the infrared signal output circuitry to emit infrared signals which will cause specific functions to occur in a specific controlled device, for operating a variety of devices to be controlled, to be supplied from outside the remote control through the receiving port of the terminal structure directly to the CPU for direct entry to the memory to enable the remote control to control various devices to be controlled upon the inputting of commands to the keys of the input. The universal remote control system further includes a data transmission system including coupling circuitry for coupling the terminal structure to a computer directly, through a modem to a telephone line, or through a television set to a television signal picked up by the television set, the coupling circuitry including a cable, a first connector for connection to the terminal structure at one end of the cable, and an interface connector at the other end of the cable for connecting directly to a computer, or through a modem and a telephone line to a computer, or to a television set which receives data in a television signal from a computer.

Abstract: Optimization techniques are implemented by means of a program analyzer used in connection with a program compiler to optimize usage of limited register resources in a computer processor. The first optimization technique, called interprocedural global variable promotion allows the global variables of a program to be accessed in common registers across a plurality of procedures. Moreover, a single common register can be used for different global variables in distinct regions of a program call graph. This is realized by identifying subgraphs, of the program call graph, called webs, where the variable is used. The second optimization technique, called spill code motion, involves the identification of regions of the call graph, called clusters, that facilitate the movement of spill instructions to procedures which are executed relatively less often. This decreases the overhead of register saves and restores which must be executed for procedure calls.

Abstract: The functions of two virtual operating systems (e.g., S/370 VM, VSE or IX370 and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors directly and through the S/88 bus. Each S/370 processor is allocated from 1 to 16 megabytes of contiguous storage from the S/88 main storage. Each S/370 virtual operating system thinks its memory allocation starts at address 0, and it manages its memory through normal S/370 dynamic memory allocation and paging techniques. The S/370 is limit checked to prevent the S/370 from accessing S/88 memory space. The S/88 Operating System is the master over all system hardware and I/O devices. The S/88 processors access the S/370 address space in direct response to a S/88 application program so that the S/88 may move I/O data into the S/370 I/O buffers and process the S/370 I/O operations. The S/88 and S/370 peer processor pairs execute their respective Operating Systems in a single system environment without significant rewriting of either operating system. Neither operating system is aware of the other operating system nor the other processor pairs.

Abstract: A "single-chip" integrated circuit device, useful in ISDN digital voice and data telephone applications, links plural channels of a data communication network with memory and CPU components of a data processing system. The device couples to the system via a bus that may be shared by other devices, and bidirectionally exchanges service information signals with the system CPU, and communication data signals with system memory. The service information includes device control information furnished by the CPU, and (channel and device) status information prepared by the device. The device contains multiple logic circuit units, operating in relative functional autonomy, and buffer memory units for storing service information and data. Units which interface to the network operate in synchronism with network communication processes. Units which interface to the system bus operate in asynchronous relation to network processes. Synchronous units which handle data are configured to form plural stage pipelines, in each direction of communication, which eases timing requirements at the bus interface. Status information is stored queued in memory unit storage spaces dedicated to the channels; each queue configured so that the system CPU can retrieve status information representing plural events in one channel in one coherent bus operation. The device is partitioned further to provide discretely separate internal paths for transferring service and data signals relative to the system. Service signal transfers to and from system CPU and directed by the CPU. Data signal transfers to and from system memory are directed by a DMA control unit in the device.

Abstract: A test architecture in a data processing system having a plurality of circuit portions, coupled via a communication bus. In the system, a dedicated test register is placed in predetermined circuit portions which each can then operate in a normal mode and a test mode. A central processing unit (CPU) may initiate a test operation in any of the circuit portions in response to software executing by writing an operand to a centralized test module. Operands are scanned into and out of a circuit portion being tested while the central processing unit is capable of performing non-test processing activites. The CPU may also test itself using a dedicated test register which can only cause the CPU to enter a test mode after the register is written to.

Abstract: In a graphic processing system, there are provided a main memory, a buffer containing a bit map memory for holding display data, a central processing unit for performing a data process involving a translation from a virtual address into a physical address so as to access the main memory, a graphic processor connected to the main memory and buffer, for processing data into a display form, and a system bus interface connected to the central processing unit, main memory and graphic processor, capable of exchanging the data among them. Furthermore, the graphic processing system includes a drawing processing unit connected to the system bus interface, for translating the virtual address into the physical address so as to access the main memory and to process the data, a bus arbitrator for performing arbitration between demands for using the interface given from the central processing unit and graphic processor, and a suspend circuit for asserting a signal requesting that the interface is released to the central processing unit.

Abstract: A power fail control system for a CPU (10) and external memory (16) utilizes a controller (18). The controller (18) is operable to detect an early power fail situation and output an interrupt to the CPU (10). The CPU (10) then goes into a power down sequence and stores critical instructions in an internal memory array (30) constituting a hidden memory during the power down sequence. An out of tolerance detector detects when the power supply voltage has fallen below a predetermined threshold and then generates reset signal. The reset signal is input to the CPU (10) to indicate that no further instructions are executable. In addition, a Chip Enable switch (46) is operated to inhibit memory control signals from being transferred from the CPU (10) to the memory (16). The internal hidden memory (30) is also inhibited from having data written thereto in the presence of the reset signal. A backup battery (22) is provided which is connected to one side of a switch. The other side of the switch is connected to the power supply voltage. When the power supply voltage falls below the battery voltage, the battery is connected to supply a current to the external memory (16).

Abstract: The design verification of the cache controller for SPUR, a shared-memory multiprocessor, is reported. The strategy was to develop a random tester that would generate and verify the complex interactions between multiple processors in functional simulation. Replacing the CPU model, the tester generates memory references by random selection from a script of actions and checks. It was easy to develop and detect over half the bugs uncovered during functional simulation. A prototype SPUR multiprocessor system that runs the Sprite operating system is being used for experiments in parallel programming. Results to data are described. >

Abstract: Stop-and-copy garbage collection has been preferred to mark-and-sweep collection in the last decade because its collection time is proportional to the size of reachable data and not to the memory size. This paper compares the CPU overhead and the memory requirements of the two collection algorithms extended with generations, and finds that mark-and-sweep collection requires at most a small amount of additional CPU overhead (3-6%) but, requires an average of 20% (and up to 40%) less memory to achieve the same page fault rate. The comparison is based on results obtained using trace-driven simulation with large Common Lisp programs.

Abstract: A method and apparatus for achieving fault tolerance in a computer system having at least a first central processing unit and a second central processing unit. The method comprises the steps of first executing a first algorithm in the first central processing unit on input which produces a first output as well as a certification trail. Next, executing a second algorithm in the second central processing unit on the input and on at least a portion of the certification trail which produces a second output. The second algorithm has a faster execution time than the first algorithm for a given input. Then, comparing the first and second outputs such that an error result is produced if the first and second outputs are not the same. The step of executing a first algorithm and the step of executing a second algorithm preferably takes place over essentially the same time period.

Abstract: A computer interconnect system uses packet data transmission over serial links connecting nodes of a network. The serial links provide simultaneous dual paths for transmit/receive. An adapter couples a CPU or the like at a node to the serial link. The adapter includes a packet memory for temporarily storing transmit packets and receive packets, along with a port processor for executing the protocol. Packets of data are transferred between the system bus of the CPU and the packet memory of a pair of data movers, one for read and one for write. The packet memory is accessed upon demand by the serial link, the port processor and the data movers, using interleaved cycles. To accommodate this access upon demand without request/grant cycles, parking registers are provided to store read or write data until a later cycle, and the data rate on the packet memory port is high enough to allow ample time for simultaneous use of both channels as well as packet processing and moving to and from the CPU.

Abstract: A digital computer system capable of processing two or more computer instructions in parallel and having a cache storage unit for temporarily storing machine-level computer instructions in their journey from a higher-level storage unit of the computer system to the functional units which process the instructions. The computer system includes an instruction compounding unit located intermediate to the higher-level storage unit and the cache storage unit for analyzing the instructions and adding to each instruction a tag field which indicates whether or not that instruction may be processed in parallel with one or more neighboring instructions in the instruction stream. These tagged instructions are then stored in the cache unit. The computer system further includes a plurality of functional instruction processing units which operate in parallel with one another. The instructions supplied to these functional units are obtained from the cache storage unit. At instruction issue time, the tag fields of the instructions are examined and those tagged for parallel processing are sent to different ones of the functional units in accordance with the codings of their operation code fields.

Abstract: A processor functioning as a coprocessor attached to a central processing complex provides efficient execution of the functions required for database processing: sorting, merging, joining, searching and manipulating fields in a host memory system. The specialized functional units: a memory interface and field extractor/assembler, a Predicate Evaluator, a combined sort/merge/join unit, a hasher, and a microcoded control processor, are all centered around a partitioned Working Store. Each functional unit is pipelined and optimized according to the function it performs, and executes its portion of the query efficiently. All functional units execute simultaneously under the control processor to achieve the desired results. Many different database functions can be performed by chaining simple operations together. The processor can effectively replace the CPU bound portions of complex database operations with functions that run at the maximum memory access rate improving performance on complex queries.

Abstract: An instruction memory apparatus for a data processing unit stores a sequence of instructions. At each instruction fetch cycle, two sequentially adjacent instructions are accessed. An instruction preprocessing unit, coupled to the internal instruction memory, combines the two sequentially adjacent instructions into a single long instruction word when the two instructions meet predefined criteria for being combined. The first of the two instructions is combined with a no-operation instruction to generate a long instruction word when the predefined criteria are not met. In that case, the second instruction [may be accessed again] is used during the next instruction fetch cycle as the first of the two sequentially adjacent instructions to be processed during that next instruction fetch cycle.

Abstract: The universal remote control system includes a universal remote control (420) comprising input elements (25) for inputting commands, infrared signal output elements (LED1-LED3) for supplying an infrared signal to a controlled device, a central processing unit (CPU) (56) coupled to the input elements and to the signal output elements, a single, non-volatile, read-write memory (54) coupled to the CPU and data coupling means including terminal means (310, 412, 504) coupled to the CPU for enabling code data for a variety of devices to be controlled to be supplied from outside the remote control (420) through the terminal means (310, 412, 504) and the CPU to the memory to set up the remote control (420) for controlling the devices to be controlled and a data transmission system for coupling a telephone line (304, 404, 604) or a television set (506) to the terminal means (310, 412, 504) of the remote control (420).

Abstract: A computer‐based controller/averager has been built for the Balle‐Flygare pulsed nozzle, Fourier transform, microwave spectrometer. We have integrated gas and microwave pulse control, digitizing and averaging, signal processing, and mirror and frequency control into an IBM PC‐AT, allowing the computer to coordinate all processes in the spectrometer. Multiple free induction decays (FIDs) are recorded for a single gas pulse without delay between digitizing sequences by continuously clocking the FID’s into multiple segments of digitizer memory. The averager fits into one of the AT’s expansion slots and has the unique feature of sharing 16 kbyte of static memory with the CPU. This gives the computer immediate access to the current average since it is already in the computer’s memory. The averaging is very fast so that the nozzle and vacuum pump remain the limiting factors for the repetition rate. Programming features are described. The spectrometer is now easier and faster to run. The increased speed and mult...

Abstract: A pipelined processing unit includes an instruction unit stage containing resource conflict apparatus for detecting and resolving conflicts in the use of register and indicator resources during the different phases of instruction execution. The instruction unit includes a plurality of resource registers corresponding in number to the number of instructions which can be processed concurrently by the processing unit. Decode circuits in response to each new instruction received by the instruction unit generate one or more sets of bit indication signals designating those resources required by the specific pipeline stage(s) executing the instruction for completing the execution of the instruction which are shared by those stages capable of completing the execution of instructions. Comparison circuits compare the set of bit indication signals for each new instruction that corresponds to resources needed by an earlier pipeline stage which in the preferred embodiment corresponds to a secondary execution unit, with the stored sets of bit indication signals for determining the presence of any resource conflict.

Abstract: A diagnostic system coupled to a programmable logic controller (PLC) via a serial data link monitors the operation of apparatus under the control of the PLC. Upon detection of a first event-initiating signal, a central processor unit (CPU) in the diagnostic system initiates a timer. The CPU then awaits receipt of a second confirming action signal representing completion of the event initiated by the first signal. The timer times out after a predetermined time interval determined by an operation parameter of the controlled apparatus. If the second confirming action signal is not received before the timer times out, the CPU provides an alarm signal to a video display such as a cathode ray tube (CRT) for displaying an alarm message. The diagnostic system includes a microprocessor controlled interface circuit for receiving data on the serial data link, a random access memory (RAM) mailbox for storing operation data of the PLC and controlled apparatus, and a main central processing unit (CPU) for determining faults in the operation of the apparatus and for providing appropriate outputs to a video generator/display arrangement for providing an alarm to an operator. The diagnostic system is independent of and passive with respect to the PLC and the apparatus it controls. The diagnostic system provides real time operating data to the operator for diagnosis.

Abstract: An electrical waveform generator and a method for electrical waveform generation are provided which includes a central processing unit (13) to first provide sequential points of a selectable waveform in digital form and store them in digital memory (15). A memory controller (14) then generates the waveform by sequencing those points through a digital to analog converter (17). Previous instruments required large memory capacity to handle all of the data points necessary to produce a wide variety of waveforms. The present invention uses mathematical notation to define and store selectable waveforms and calculates the data points when a curve is selected or defined for use. Memory controller (14) uses concatenated looping during the sequencing of points to the converter (17) for the purpose of making the data memory (15) more efficient. The single waveform generator of the present invention may be used in many of the various applications of waveform generators including automated test equipment having industry standard communication buses for control.

Abstract: A method for monitoring the sequence of instructions executed by a central processing unit. When a branch instruction is executed, the central processing unit generates a representative interface signal. When a jump instruction is executed or an exception occurs, the central processing unit displays representative information on the external memory interface.

Abstract: A method of exchanging information in a processing system including the steps of issuing a clock synchronizing instruction from an operating system, holding the clock synchronizing instruction in a communication information holding unit, suppressing the updating of internal state information in a first arithmetic unit in response to the holding signal, outputting a communication demand signal from the communication information holding unit to a system control unit, freezing the updating of the calendar clock values in respective first and second arithmetic processing units, receiving in the system control unit the first clock value from the first arithmetic processing unit, storing the first calendar clock value in the second arithmetic processing unit, issuing a restarting signal to the arithmetic processing units, and issuing a microprogram actuating instruction to the arithmetic processing units from the system control unit.

Abstract: A computer system which includes a central processing unit including a first processing unit that performs basic processing functions and a co-processing unit that performs multiple specialized processing functions concurrently with the first processing unit, an arrangement for detecting the occurrence of a function causing an exception in a result produced by the coprocessing unit, an arrangement for specifying to the first processing unit any exception in a result produced by the coprocessing unit, an arrangement for using the first processing unit to implement any function which causes an exception in a result produced by the co-processing unit, an arrangement for storing the identification of the instruction being handled by the first processing unit when a function causing any exception in a result produced by the co-processing unit occurs, and an arrangement for determing the instruction which produced the exception.

Abstract: A system and method are disclosed for computer implementation of a plurality of diverse commercial functions, the system comprising a central processing unit (CPU), a first plurality of storage modules each individually addressable by the CPU and containing what is termed a "component subprocess", and a second plurality of storage modules, each also individually addressable by the CPU and containing what is termed a "log point". Planner interactive means are provided and furnished by the CPU from further storage of the system with menus for the planning of what are termed system "products". Such menus present for selection various components which can be implemented. Responsively to planner component selection, for each component selected by the planner, the CPU responds by displaying the component processes associated with such component and the planner accumulates desired products by selecting component processes. Again from system storage, the CPU furnishes, for display and selection, system log points, which are predefined conditions in a component process which collect transaction information. In providing products for use, the CPU obtains log points and component subprocess from storage in sequences according with the component processes of the products.

Abstract: A highly-parallel processing system in which a number of processing elements are interconnected by a network, and are also connected to a system bus and controlled by a central processing unit. Each processing element includes a memory, and all of the memories in the processing elements form at least part of the memory available to the CPU. The processing elements normally execute programs in MIMD mode, and the CPU or another unit can interrupt them to execute a SIMD instruction. The network allows for transmission of variable length messages and also for combining messages when received at a common processing element.

Abstract: An architecture for providing hardware compression/decompression with ECC to data flow in a computer system utilizes a hardware implementation of the compression/decompression circuit in a peripheral adapter of one of many peripheral devices. Error correction coding is provided by software in the host RAM. The compression/decompression circuit can be located in the periphery and can service a number of peripheral devices. The CPU and DMA controller in the host computer are capable of providing concurrent processing for hard disk operation, peripheral control (such as a tape or a modem), compression/decompression of data, and error correction coding of the compressed data. This significantly speeds up the performance of the computer system.

Abstract: A monolithically integrated microcomputer clocked at a processor clock rate includes a clock generator in the form of an RC oscillator being synchronizable by external signals for controlling at least one functional unit operating asynchronously with the processor clock rate. The RC oscillator has a frequency-determining resistor and a frequency-determining capacitor being monolithically integrated. The frequency-determining capacitor is formed of a plurality of switchable capacitors to be interconnected to make a total capacitor with a variable size. Registers are each connected to a respective one of the capacitors for defining a switching state of the switchable capacitors. A central processing unit is connected to the registers for adjusting the frequency of the clock generator by setting the registers.

Abstract: An architecture for a central processing unit (cpu) provides for the extraction of low-level concurrency from sequential instruction streams. The cpu includes an instruction queue, a plurality of processing elements, a sink storage matrix for temporary storage of data elements, and relational matrixes storing dependencies between instructions in the queue. An execution matrix stores the dynamic execution state of the instructions in the queue. An executable independence calculator determines which instructions are eligible for execution and the location of source data elements. New techniques are disclosed for determining data independence of instructions, for branch prediction without state restoration or backtracking, and for the decoupling of instruction execution from memory updating.