Abstract: A system and method for controlling the security of data in a central high speed data processing unit (CPU) by electronically sensing and comparing all operating or control statements coming into the CPU from terminal devices with a vocabulary of all statements unacceptable for security reasons which unacceptable statements are stored in a remote secondary computer system. The security of the data is also controlled by electronically sensing and comparing all operating and problem steps loaded into the CPU from library devices with a collection of identifiers known to identify all correct versions. The reaction to security dangers found in either sensing and comparing method is to exert predetermined counteraction to preclude unauthorized removal, alteration, destruction or inspection of problem data and/or procedures. The system includes a plurality of sensors which monitor operating control statements, operating and problem steps or procedures and physical switches on the CPU control panel. The remote secondary computer analyzes the sensor output and responds by a predetermined counteraction which includes initiating an alarm and descriptive printout at a remote location and indicating the source and severity of any security violation. Further, the secondary computer may interrupt the CPU and drain any illegal control statements and prevent the loading of the operating process and problem steps.

Abstract: Cyclic queuing systems have been proposed by several authors in the study of the behavior of multiprogrammed computer systems. Programs in the system wait for service at the central processor unit CPU; then, after page fault or input-output request at a data transmission unit DTU, the process repeats until the program completes. Semi-Markov analysis of such systems, based on the apparently plausible assumption of independently but exponentially distributed CPU burst time, and independent, but nearly constant DTU tune may be conducted. This paper presents some very simple approximations based on a continuous-state approximation-the simple diffusion with two reflecting barriers-to describe the CPU utilization. Computational experience from which the quality of the approximations can be assessed is reported.

Abstract: A data processing system using a high speed buffer storage to interface main storage with a central processing unit. Algorithms for the purpose of prefetching the next sequential line from main storage to the high speed buffer and for replacement of existing lines in the high speed buffer may be dynamically modified relative to the type of program being executed by the use of a system console unit.

Abstract: Apparatus for fetching instructions to an instruction register of a central processing unit, including instruction buffers for storing instructions prior to their execution in the CPU (look-ahead) and apparatus for storing instructions which have been executed in the CPU (look-behind) in anticipation of their further use in, for example, programming loops. The look-behind apparatus comprises a multi-word buffer with its associated data register. The buffer data register, in addition to its function as part of the look-behind apparatus, also provides an additional level of look-ahead.

Abstract: A digital processor includes: a main read only memory store providing instruction and constant data signals; a random access memory store for storing variable data signals; an input/output port unit communicating with the terminal devices; an interrupt address generator controlling the interrupt priority for the terminal devices; an arithmetic and logical unit; an instruction decoding and execution unit controlled according to instructions in a fast access read only memory store address controlled by the instruction signals in the main read only memory store for controlling the operations of the digital processor; and a group of working and general registers for buffer storage of digital signals. Interconnections between the units of the processor are through a single bidirectional data bus. Process steps control the operation of the processor according to an instruction format.

Abstract: A system for transferring information between a plurality of memory banks in which there are provided a plurality of memory banks each having the same performance and capacity. At least one of the memory banks serves as an operating memory bank while at least one of the other memory banks serves as a standby. Processing circuit means including a central processing unit and a data channel unit are provided to utilize the contents of the memory banks, and a memory control means controls the transfer of data to be processed from the memory banks to the utilizing circuit means. A memory to memory transfer circuit means is operable to transfer all of the information from the operating memory bank to the standby memory bank in a manner which prevents loss of information during the switching of the memory banks, whereby the standby memory bank then becomes the operating memory bank.

Abstract: A computing system includes a central processor unit (CPU) integrated on a monolithic chip in combination with external memory units. The CPU includes a parallel arithmetic logic unit (ALU) and an internal random access memory interconnected on a common parallel buss with an instruction register. The random access memory defines general purpose data registers, program and memory address registers, and a multi-level program address stack. Timing circuitry in the CPU enables the external memory to be either serial or random access. A single input to the CPU enables a single output which is effective to interrupt CPU operation so that external instructions may be inserted. In one embodiment two CPUs share a common external memory, and a method is provided for simultaneously executing two separate programs using a common memory.

Abstract: This paper investigates some of the effects of varying the number of central processing units (CPU's) available to a multiprogramming system both when parallel processing of a single task (multitasking) is allowed and is not allowed. The variables investigated are those that would be expected to control the CPU queue length distribution and include the degree of multiprogramming, CPU service discipline, CPU service distribution, the degree of cooperation between processors engaged in multitasking, and the ratio of CPU to I/O service capacity. The computer systems are modeled by queueing networks. Analytic results are displayed in many cases with supplementation by numeric and simulation solutions when convenient or necessary. It is demonstrated that under properly defined conditions doubling the number of CPU's in a system can more than double throughput. The effectiveness of multitasking in improving throughput is found to be fairly small if the degree of multiprogramming ranges from modest to high.

Abstract: The problem of determining page size in a page on demand system is discussed in detail in this paper. After having introduced the problem, the effect page size may have on various system performance measures is reviewed based on measurements of program behaviour and on simple models of system behaviour. This discussion is followed by a detailed study of the effect of the choice of page size on the efficient utilization of primary memory space. The wasted space-time integral (WSTI) of primary memory space is selected as a measure of this utilisation and a new model of program and system behaviour is used to compute the WSTI for different secondary memory devices (drum, ECS and LCS) and different system behaviour parameters such as the time spent in supervisor mode by the operating system to initiate a page transfer, the time spent in the CPU queue by a program which has recovered from a page fault before it receives the attention of the CPU, the global page fault rate (or arrival rate at the secondary storage devices used for paging) and other factors. The influence of each of these factors is discussed and analyzed, and the conditions under which one or another of these dominates the problem is identified. In the Appendix, one of the problems posed by our model, the use of approximate formulae for fragmentation which remain valid for a large class of probability distribution functions of program size, is analyzed in detail. Some tests are developed for the validity of these formulae.

Abstract: A microprogrammable peripheral controller is provided in which the control store microinstruction format is compatible with the read/write memory data word format and the architecture is compatible with character oriented peripheral data formats. The controller is provided with a processor which enables word transfers in a single operation. The processor also has the capability of performing a large repertory of arithmetic and logic microinstructions, but this is made economical by limiting such operations, in general, to byte length operands. With this processing capability, the primary controller control functions can be performed economically for a wide range of perioherals. A common interface is provided for data and control information transfers between the controller and both peripheral devices and central processor ports. In general, adaptor units are required to provide compatibility between the controller and the CPU ports and peripheral interfaces, to provide data buffering, to support multiplexing and for any other special functions. The primary feature to which this disclosure is directed is processor architecutral features which effectively eliminate processor execution time for performing branching operations whereby processing speed is effectively increased by a factor of more than one third for many if not all control store programs. Controller economy and reliability is further advanced by the use of dual arithmetic/logic modules which serve as redundant elements for byte operations and word transfer elements for word transfer operations.

Abstract: A data processing system includes a main memory, a central processing unit, an input-output processing unit and a scientific processing unit. The central processing unit is operative to fetch each of the instructions of a program stored in main memory and then determines whether the execution of the instruction by either the input-output processing unit or the scientific processing unit can be overlapped with the central processing unit's fetching of a next instruction of the program. The scientific processing unit includes storage which enables the unit to execute certain types of instructions it receives from the central processing unit independently of the central processing unit. when the central processing unit determines that it has fetched one of these types of instructions, it begins immediately fetching a next instruction after it has delivered to the scientific processing unit information the scientific unit requires for executing the instruction. The system also includes apparatus which allows an operator access to the scientific unit storage for checking purposes.

Abstract: The problem of determining page size in a page on demand system is discussed in detail in this paper. After having introduced the problem, the effect page size may have on various system performance measures is reviewed based on measurements of program behaviour and on simple models of system behaviour.This discussion is followed by a detailled study of the effect of the choice of page size on the efficient utilization of primary memory space. The wasted space-time integral (WSTI) of primary memory space is selected as a measure of this utilisation and a new model of program and system behaviour is used to compute the WSTI for different secondary memory devices (drum, ECS and LCS) and different system behaviour parameters such as the time spent in supervisor mode by the operating system to initiate a page transfer, the time spent in the CPU queue by a program which has recovered from a page fault before it receives the attention of the CPU, the global page fault rate (or arrival rate at the secondary storage devices used for paging) and other factors. The influence of each of these factors is discussed and analyzed, and the conditions under which one or another of these dominates the problem is identified.

Abstract: This paper discusses the architecture of the FCPU (Flexible Central Processing Unit) developed by the Datasaab sector of Saab-Scania AB. This medium-scale asynchronous microprocessor is capable of efficiently emulating a wide variety of past, present and future target languages. The global architecture and microinstruction processing strategy are presented. The general properties of the high level oriented microprogramming language are discussed and a micro-programming example is presented which illustrates an important application of the microprocessor.

Abstract: A central processor unit under the control of microprogram words retrieved from a storage facility in sequence. A control section in each microprogram word contains information used to define data paths while an address portion identifies the location of the next microprogram word in sequence. A buffer register receives each microprogram word, the address passing through a modification circuit. If a first microprogram word sets up branching conditions within the central processor unit, other circuitry establishes an address offset which is applied to a base address contained in the next microprogram word to thereby alter the location of the following microprogram word. Thus, any microprogram word which can produce a branch must be followed with an other microprogram word which does not depend upon the branch conditions, but which contains a base address.

Abstract: A computer system executes instructions for an I/O device not attached to the system. A quasi I/O attachment device is responsive to the commands for the unattached I/O device and generates an interrupt condition. The interrupt condition causes the command instructions for the unattached I/O device to be translated to command instructions for an I/O device connected to the computer system. The I/O device attached to the system performs the designated operation and generates associated I/O device status data. This associated I/O device status data is translated into I/O device status data for the unattached I/O device and thus permits a program for operating an unattached I/O device to operate instead an I/O device attached to the system which otherwise could not be operated by that program. A second embodiment performs the emulation of the unattached I/O device remotely of the central processing unit in the computer system.

Abstract: A hierarchial memory/storage system in which the data is transferred between a high speed local storage, responsive to the processing unit of the computer, and a plurality of higher levels of larger low speed storage wherein data available to the central processing unit is shifted between the various levels of the hierarchial system in a highly efficient manner. In operation, the system in responding to the central processing unit for making available data in the high speed lowest hierarchial level, will seek out the instant lowest buffer memory/storage level containing the required information, form a path of expendable blocks or page frames in the various buffer levels from the adjacent lower level down to the H1 level, shift any updated information in the path of expendable pages to the off-the-path pages at appropriate higher levels utilizing the successively lengthened cleared upper path for forward and rearward transfer of blocks or pages within the memory system, and subsequently, when the complete clear path of expendable blocks or page frames is formed, transfer and filter the called-for data segments through the path to the level of the hierarchial memory responsive to the processing unit of the computer.

Abstract: A control unit for a magnetic tape subsystem of a data processing system includes a maintenance facility. This maintenance facility permits the exercise of the magnetic tape subsystem for diagnostic and maintenance purposes. The control unit is of the microprogram type, in which a control memory contains micro orders which control the operation of the magnetic tape units. The maintenance facility exercises the tape subsystem in two different manners-with the Input/Output command language of the CPU or with the micro order language of the control unit. This can be performed while the magnetic tape subsystem is switched offline to the CPU, or time-multiplexed with the operational usage of the magnetic tape subsyste by the CPU. The control unit includes a random access memory connected in parallel with the control memory. In the diagnostic mode, micro orders are transferred from a magnetic tape unit to the random access memory. Then, sequences of these micro orders are performed in the same way that micro orders stored in the control memory are otherwise executed in order to perform diagnostic testing. The data path transferring the micro orders from the magnetic tape unit to the random access memory is a simple one which bypasses the normal circuits which might otherwise introduce errors into the diagnostic micro orders. Amplitude sensors, which are otherwise used for error detection and correction, are connected to majority circuits which produce outputs when the amplitude sensors indicate that a majority of the data tracks are written with a ''''1.'''' In this manner, very reliable micro orders are obtained for performance of the diagnostic testing function. The maintenance facility provides full micro order control over a Field Engineer Buffer. Data and commands are loaded into a fetched from any buffer position under manual switch control or microprogram control.

Abstract: A Read-Only Memory device in the CPU of a microprogrammable computer contains a diagnostic program suitable for self-testing the computer. A microprogram for loading this diagnostic program from the Read-Only Memory device into Main Memory is contained in the Control Memory of the CPU. When required, the diagnostic program is loaded into Main Memory and executed thus allowing for the testing of a computer without the need of operational peripherals.

Abstract: Apparatus for two controller execution of verification and diagnostic procedures in a data processing unit. The CPU and IOC subsytems of the data processing unit each contain control apparatus which can be used to manipulate the apparatus of the associated subsystem as well as the apparatus of the nonassociated subsystems. The control apparatus of each subsystem has access to error-detection circuitry and a plurality of registers in both subsystems so as to have available the results of apparatus manipulation. The detection of a fault condition in one subsystem can be analyzed by the second subsystem without ambiguity caused by the fault condition itself. The control apparatus of both subsystems can cooperate to test interacting portions of the subsystems.

Abstract: The results are presented of an analysis of a probabilistic model of a multiprogrammed computer system with a two-level storage system in which there is sequential dependency of accesses between the devices. Expressions are obtained for the long-run probability that both the CPU and each of the storage devices are busy. Some numerical results are given which quantify the gains in CPU utilization obtainable by multiprogramming in the presence of this type of storage system.

Abstract: A synchronous computing system includes a central processor unit interconnected with external memory units. The processor is integrated monolithically on a single chip and includes a plurality of data registers, a parallel arithmetic logic unit and an instruction register interconnected by a common parallel buss. A control section of the processor synchronizes internal operation of the processor and also system operation, and includes a plurality of programmable logic arrays to provide a versatile method of accommodating different instruction sets, sequences of operation, and instruction cycle duration. The arrays reduce the number of interconnects required and increases utilization of semiconductor material for forming active devices. This is a continuation of application Ser. No. 176,665, filed Aug. 31, 1971, now abandoned.

Abstract: The ISP (for Instruction Set Processor) notation was developed for a text [Bell& Newell, 1971] to precisely describe the programming level of a computer in terms of its Memory, Instruction Format, Data Types, Data Operations, Interpreting a Specific Instruction Set.

Abstract: This paper presents an approach to achieve high central processing unit (CPU) availability with an increase in performance by multiprocessing on an instruction stream level, where instruction fetching/executing is done by closely coupled processing units (PU's). A treatment is given of the necessary control for coordination of the PU's. This processing interaction is accomplished by microcode shared by the units. Either PU can be interchanged in any processing function, and the total processing complex comprises a single CPU as far as the external world (i. e., the operating system and user's programs) is concerned. The results of manual simulation on two sample problems are given along with a comparison of processing with a single PU and with another instruction stream multiprocessing scheme presented in [4].

Abstract: The computer processor comprises a plurality of registers and an arithmetic logic unit along with interfaces with other units of a data processing system connected as sources and sinks to one data bus and one address bus Each source for a bus has leads from the output of a register or a set of interface leads connected to inputs of AND function gates with the gates for a selected source enabled by a control signal, and the outputs of the respective bits of the AND gates of the several sources are connected to OR function gates, the outputs of which comprise the bus A register or set of interface leads acting as a sink has the bus connected to the inputs of AND function gates whose outputs are connected to the inputs of the register or interface leads, and the gates for a sink are enabled by a sink select signal Each of the buses also has its leads connected back as source leads to AND function gates which are enabled by a LATCH signal, thereby effectively making the bus act as a register For certain instructions of the order set, either or both buses may be latched during the processing to retain information while the source register is used for other purposes

Abstract: An electronic computer system having a main functional unit and a plurality of sub-functional units, such as a memory unit, a function generator unit, etc., with all of the functional units being supplied with a key code signal from a single keyboard unit through a common key code bus line. All of the functional units give instruction signals to an arithmetic unit through a common instruction bus line.

Abstract: Circuits for the improved operation of microprogrammable computers are described. This improvement is accomplished by providing a set of read-only memory devices for storing the micro-code for all combinations of arithmetic logic unit function, carry bit and file register address than can be specified by an instruction word executed from Main Memory. In a universal microprogram designed to execute that family of Main Memory instructions that differ only in the functions specified above, the instruction word is used to address the read-only memory devices, the micro-code output of which is used to control the file, carry in bit and arithmetic logic unit. Through the use of these circuits a family of instructions may be executed by a single microprogram and at no increase in execution time over that required for the execution of a microprogram dedicated to a single instruction.

Abstract: A description of the Burroughs Operational Systems Simulator (BOSS) is given. A BOSS process is shown which models a system disk call. The concept of embedded processes is introduced, exemplified and expanded using a model for retrieval in a message switch. The modeling of virtual memory in a computer system is discussed. A process sets the parameters for the use of a central processing unit (CPU) and then calls an embedded process that handles the events leading to CPU action. All events involved with the model for automatic search for core space and memory overlay are shown.

Abstract: The objective of this brief paper is to point out an often overlooked central issue facing the computer manager today and to suggest a comprehensive technique to improve management and utilization of large-scale computer systems.In the early days of computing the resources of a system could be measured in terms of a few hardware parameters such as memory size, speed of arithmetic and logical operations, and speed and complexity of I/O devices. Management was a matter of scheduling time for each user, often on a first come first served basis. This type of regime is still prevalent at smaller computer installations today. Larger installations, typically 360/65 and above running under OS/360, now use some form of multiprogramming to take advantage of hardware economies of scale with overlapped memory fetch, compute, and I/O operations. In the past, most of the cost of a computer installation was the CPU and core memory, while today it is the almost bewildering array of I/O devices.

Abstract: A calculator comprising a conventional cardinal calculator having an input keyboard unit, a central processing unit input and output, and an output display unit wherein the connections on the central processing unit input from all terminals on the input keyboard unit are shifted down to that of the next lower numeral in the central processing unit input. The connections on the output display unit from all terminals on the central processing unit output are shifted up to that of the next upper numeral in the output display unit resulting in an ordinal calculator for producing an ordinal number sum, difference, product, or quotient answer from an input and subsequent computation of two ordinal numbers. With the addition of a gang switch for shifting all these connections by one terminal, a cardinal-ordinal calculator results for utilizing either or both cardinal and ordinal numbers. Two modifications of the ordinal calculator and two modifications of the cardinal-ordinal calculator are disclosed. For computer use it is only necessary that the computer program instruct the operator when to shift from cardinal to ordinal operation or vice versa.