Topic
Capability-based addressing
About: Capability-based addressing is a research topic. Over the lifetime, 15 publications have been published within this topic receiving 1296 citations.
Papers
TL;DR: It is shown that a large number of errors can be detected by monitoring the control flow and memory-access behavior and two techniques for control-flow checking are discussed and compared with current error-detection techniques.
Abstract: Concurrent system-level error detection techniques using a watchdog processor are surveyed. A watchdog processor is a small and simple coprocessor that detects errors by monitoring the behavior of a system. Like replication, it does not depend on any fault model for error detection. However, it requires less hardware than replication. It is shown that a large number of errors can be detected by monitoring the control flow and memory-access behavior. Two techniques for control-flow checking are discussed and compared with current error-detection techniques. A scheme for memory-access checking based on capability-based addressing is described. The design of a watchdog for performing reasonable checks on the output of a main processor by executing assertions is discussed. >
617 citations
12 May 1981
TL;DR: The IBM System/38 provides capability-based addressing and support is divided among architectural definition, microcode, and hardware to minimize overhead for this function.
Abstract: The IBM System/38 provides capability-based addressing. This paper describes how support is divided among architectural definition, microcode, and hardware to minimize overhead for this function.
73 citations
10 Jan 1989
TL;DR: Those features of the MONADS computer architecture which support object-oriented programming are outlined and how objects are efficiently supported in the system’s large persistent uniform virtual memory is shown.
Abstract: The paper outlines those features of the MONADS computer architecture which support object-oriented programming. It begins by describing the MONADS view of objects and then shows how objects are efficiently supported in the system’s large persistent uniform virtual memory. Direct architectural support for objects in stack and heap segments is discussed, and the idea of module capabilities and module call segments as a technique for efficiently invoking the operations of persistent major objects in a protected way is also described. Following a description of the underlying memory structure and its use of capability based addressing, the paper concludes with a short discussion of garbage collection, local area networks and a massive memory version of the hardware.
42 citations
TL;DR: The SWARD architecture, an experimental higher-level architecture, contains the naming and protection concept of capability-based addressing, which led to a set of problems that led to the implementation of capabilities by the processor.
Abstract: The SWARD architecture, an experimental higher-level architecture, contains the naming and protection concept of capability-based addressing. After discussing the merits of capability-based addressing, its general representation in the SWARD architecture is discussed. The initial representation of capability-based addressing in the architecture led to a set of problems; these problems are described, as well as their solutions. Finally, the implementation of capabilities by the processor is discussed.
30 citations
TL;DR: An architecture is presented which incorporates capability based addressing and memory tagging features and it defines three kinds of mechanisms for the implementation of object types, which correspond to as many different levels of abstraction.
Abstract: An architecture is presented which incorporates capability based addressing and memory tagging features. It defines three kinds of mechanisms for the implementation of object types, which correspond to as many different levels of abstraction. At the lower level, there are the machine types, the operations of which are implemented by machine instructions. At the upper level, there are user types, the operations of which are concretized by means of software routines. The intermediate level is that of predefined types; in this case, too, the operations are supported by software routines, but their efficiency of execution is much greater than is usually to be found in operations of user types. However, one drawback is that these routines should be proved to be correct, as they have a potential for corrupting the integrity of the whole protection system.
23 citations
Related Topics (5)
Performance Metrics
| Year | Papers |
|---|---|
| 2016 | 1 |
| 2003 | 1 |
| 1996 | 1 |
| 1995 | 1 |
| 1994 | 1 |
| 1989 | 1 |