C-element

Abstract: Various applications have demonstrated that asynchronous circuits have great potential for energy-efficient and high-performance design. One of the primitives used in asynchronous control circuits is the C-element. Analytical delay and energy models are presented and applied to the most popular complementary metal-oxide-semiconductor (CMOS) implementations of the C-element. Optimization of these implementations are discussed. The implementations are also compared using simulations. The simulation results are in good agreement with the analytical predictions.

Abstract: Many high energy physics and nuclear science applications require sub-nanosecond time resolution measurements over marry thousands of detector channels. Phase-locked loops have been employed in the past to obtain accurate time references for these measurements. An alternative solution, based on a delay-locked loop (DLL) is described. This solution allows for a very high level of integration yet still offers resolution in the sub-nanosecond regime. Two variations on this solution are outlined. A novel phase detector, based on the Muller C element, is used to implement a charge pump where the injected charge approaches zero as the loop approaches lock on the leading edge of an input clock reference. This greatly reduces timing jitter. In the second variation the loop locks to both the leading and trailing clock edges. In this second implementation, software coded layout generators are used to automatically layout a highly integrated, multi-channel, time to digital converter (TDC). Complex clock generation can be achieved by taking symmetric taps off the delay elements. The two circuits, DLL and TDC, were implemented in a CMOS 1.2 /spl mu/m and 0.8 /spl mu/m technology, respectively. Test results show a timing jitter of less than 35 ps for the DLL circuit and better than 135 ps resolution for the TDC circuit.

Abstract: A multi-input Muller C-element has frequently been used for joining signal transitions or completion time detection in self-timed circuits. An n-input Muller C-element design which uses the multilevel logic design technique and has a symmetric format for any integer n >or=2 is presented. In comparison with series-parallel MOS structure implementations and C-element tree implementations, the present design has fewer restrictions in terms of n, less path delay, less delay variance from inputs to output, and less area consumption. Experimental validation based on an industrial standard cell library is presented. >

Abstract: This paper presents and analyzes a high performance latch tolerating single event upsets (SEU) in 45 nm CMOS technology. The internal nodes of the latch are immune to SEUs by combining Muller C-elements with dual modular redundancy and interlocked feedback. The output nodes are SEU resilient and allow a recovery to the correct logic value when an SEU occurs at output nodes. The power dissipation, propagation delay and critical charge of the proposed SEU-tolerant latch are evaluated and discussed with SPICE simulations. The simulation results show that the proposed latch achieves a better tradeoff among soft error rate, delay, power and area than previous hardened latches. On average the HPST latch requires 70.31 % area overhead, but improves the critical charge by 71.05 % and reduces the power delay product by 51.96 %. It is thus an excellent solution for applications requiring both high performance and high reliability. Monte Carlo simulation also verifies the robustness of the proposed latch in presence of process, temperature and voltage (PVT) variations.