Bus analyzer

Abstract: A system of the present invention tests the design of a universal serial bus (USB) smartcard device and includes a bus analyzer for running test cases to generate USB bus traffic. A processor is operatively connected to the bus analyzer for receiving and transforming data about USB traffic into a selected data format that is usable across different smartcard development environments.

Abstract: The present invention provides a portable SCSI bus analyzer (PSBA) that is less bulky and less expensive than the known prior art systems. The PSBA provides a portable device that may be connected to a SCSI port of a computing system and may act as a target or initiator on the SCSI bus. The PSBA gathers trace data of data transactions occurring over the SCSI bus and stores them either in a storage device of the computing system or, in a preferred embodiment, on a removable memory card inserted into a memory card interface of the PSBA. The PSBA gathers the trace data for a predetermined period of time. At the end of the trace, or test, the PSBA may be removed from the computing system and transported to another location where an analysis device is provided with the trace data. The analysis device analyzes the trace data in order to determine potential sources of error in the operation of the computing system.

Abstract: Personal digital assistants are lightweight, inexpensive, and ubiquitous. Furthermore, they have desktop class operating systems features supported by industrial strength development tools. These devices provide an ideal platform for deploying a practical platform for I2C bus analysis. In this paper, we propose a low-cost, highly portable I2C bus analyzer on a PalmOS based PDA. We describe the hardware interface, the supporting libraries, and the PalmOS-complaint application. The proposed approach is flexible and supports the creation of additional bus analyzer applications by third parties. The example bus analyzer application described here provides three operating modes, passive snooping, active bus mastering, and active slave device emulation. Each mode function over number of user-selectable data rates.

Abstract: A Bus Analyzer Unit (BAU) for performing trace analysis on either or both the global bus (GBus) or the I/O bus of a semiconductor chip. The BAU has a GBus trace unit and an I/O bus trace unit, each with its own trace logic. Each unit has filters and comparators which determine what data is recorded and when it is recorded. Trace data recorded by the units is written to a programmable, circular trace buffer in local memory or an SDRAM. Each trace unit has two registers holding the start and end addresses of the trace buffer. Each unit has a next address register containing the next address to which data may be written. As data is written, the next address register is incremented. When the next address register equals the value in the end address register, the next address register is reloaded with the address in the start register.