Bus

Abstract: A reconfigurable computer network interface device (10) includes a reconfigurable controller (12), reconfigurable bus interface (22), and reconfigurable transceiver (14). The device (10) also includes a configuration control arrangement (20) and on-board memory (16) for storing configuration instructions. The preferred form of the invention also includes an arrangement for receiving configuration instructions from an external source. The reconfigurable bus interface (22) may be configured by hardware set-up and operational software instructions to emulate a bus interface for any of a number of different computer bus architectures. A bus adapter (26) connects between a bus port (39) associated with the reconfigurable bus interface (22) and the computer bus to provide the physical connection between the device (10) and the host computer. The reconfigurable transceiver (14) is reconfigurable by hardware set-up and operational software instructions to communicate in any one of a number of different network hardware protocols. A media connector (24a, 24b) cooperates with a transceiver port (23a, 23b) associated with the reconfigurable transceiver (14) to provide the physical connection between the device (10) and network medium (32a, 32b). The reconfigurable controller (12) is configurable by hardware set-up and operational software instructions to communicate in any of a number of different software protocols. Thus, the reconfigurable computer network interface device (10) may operate as a network card, bridge, router, brouter, or gateway between substantially any type of computer and any type of computer network.

Abstract: A bus system is described that minimizes clock-data skew. The bus system includes a data bus, a clockline and synchronization circuitry. The clockline has two clockline segments. Each clockline segment extends the entire length of the data bus and is joined to the other clockline segment by a turnaround at one end of the data bus. The clockline ensures that clock and data signals travel in the same direction. Synchronization circuitry within transmitting devices synchronizes data signals to be coupled onto the data bus with the clock signal used by other devices to receive the data.

Abstract: A bus powered hub having a switch to control power distribution in a universal serial bus A single switch is used to control power distribution to a number of peripherals connected to the bus powered hub When the bus powered hub is initialized, the switch is activated thus providing power to the peripheral devices coupled to the bus powered hub The system subsequently queries the peripheral devices to determine if an illegal configuration exists If an illegal configuration exists, the system generates an error message to the user indicating the nature of the illegal configuration If no illegal configuration exists, the system initializes the various peripheral devices

Abstract: An arbitration system for a shared address, data and control bus provides burst mode operations for transferring data between a peripheral device and memory via a bus master. The arbitration system is responsive to high priority bus activities, such as memory refresh cycles and DMA cycles to temporarily transfer control of the shared bus from the bus master to a circuit controlling the high priority activity. After the high priority activity is completed, the arbitration system returns control of the shared bus to the bus master so that the associated peripheral device may continue operating in the burst mode. This transfer of control occurs without requiring the time overhead of arbitrating priority between bus masters having active bus requests. The arbitration system further includes timing circuits to assure that a bus master transferring data in the burst mode does not retain control of the shared bus for an excessive amount of time.