Topic
Buffer underrun
About: Buffer underrun is a research topic. Over the lifetime, 1130 publications have been published within this topic receiving 19095 citations. The topic is also known as: Buffer Underwrite ('Buffer Underflow').
Papers published on a yearly basis
Papers
Patent•
IBM1
TL;DR: In this paper, a data buffer is coupled to a mass storage unit for storing up to M of the temporally-ordered segments, wherein M is less than N. The data buffer manager schedules the transfers in accordance with at least a predicted time that an individual one of temporally ordered segments will be required to be output from the data buffer.
Abstract: A data storage system includes a mass storage unit storing a data entity, such as a digital representation of a video presentation, that is partitioned into a plurality N of temporally-ordered segments. A data buffer is bidirectionally coupled to the mass storage unit for storing up to M of the temporally-ordered segments, wherein M is less than N. The data buffer has an output for outputting stored ones of the temporally-ordered segments. The data storage system further includes a data buffer manager for scheduling transfers of individual ones of the temporally-ordered segments between the mass storage unit and the data buffer. The data buffer manager schedules the transfers in accordance with at least a predicted time that an individual one of the temporally-ordered segments will be required to be output from the data buffer. When employed with a media streamer (10) distributed data buffer management techniques are employed for selecting blocks to be retained in a buffer memory, either in a storage node (16, 17) or in a communication node (14). These techniques rely on the predictable nature of the video data stream, and thus are enabled to predict the future requirements for a given one of the data blocks.
412 citations
Patent•
21 Nov 1990TL;DR: In this article, the authors propose a method of controlling congestion in a virtual circuit packet network, where a packet buffer is assigned to each virtual circuit at each node into which incoming packets are stored and later removed for forward routing.
Abstract: A method of controlling congestion in a virtual circuit packet network. A initial packet buffer is assigned to each virtual circuit at each node into which incoming packets are stored and later removed for forward routing. If a larger buffer is desired for a virtual circuit to service a larger amount of data, then additional buffer space is dynamically allocated selectively to the virtual circuit on demand if each node has sufficient unallocated buffer space to fill the request. In one embodiment, the criterion for dynamic allocation is based on the amount of data buffered at the data source. In alternative embodiments, the criteria for dynamic allocation may be further based on the amount of data buffered at each node for a virtual circuit and the total amount of free buffer space at each node of a virtual circuit. Signaling protocols are disclosed whereby data sources and virtual circuit nodes maintain consistent information describing the buffer allocations at all times.
198 citations
Patent•
IBM1
TL;DR: In this article, a video server is provided with buffer manager which balances the loads on the various "movie storage" elements of video server by preferentially buffering streams on highly loaded storage elements, which takes place only when the storage element load increases due to the arrival of a new request or when buffer becomes available due to pausing or stopping of an old request.
Abstract: A video server is provided with buffer manager which balances the loads on the various "movie storage" elements of a video server by preferentially buffering streams on highly loaded storage elements. The allocation of buffer takes place only when the storage element load increases due to the arrival of a new request or when buffer becomes available due to the pausing or stopping of an old request.
165 citations
Patent•
2 Nov 2004TL;DR: In this article, a per-flow dynamic buffer management scheme for a data communications device is presented, where the header information for each packet is mapped into an entry in a flow table, with a separate flow table provided for each output queue.
Abstract: The present invention provides a per-flow dynamic buffer management scheme for a data communications device. With per-flow dynamic buffer limiting, the header information for each packet is mapped into an entry in a flow table, with a separate flow table provided for each output queue. Each flow table entry maintains a buffer count for the packets currently in the queue for each flow. On each packet enqueuing action, a dynamic buffer limit is computed for the flow and compared against the buffer count already used by the flow to make a mark, drop, or enqueue decision. A packet in a flow is dropped or marked if the buffer count is above the limit. Otherwise, the packet is enqueued and the buffer count incremented by the amount used by the newly-enqueued packet. The scheme operates independently of packet data rate and flow behavior, providing means for rapidly discriminating well-behaved flows from non-well-behaved flows in order to manage buffer allocation accordingly. Additionally, the present invention adapts to changing flow requirements by fairly sharing buffer resources among both well-behaved and non-well-behaved flows.
156 citations
Patent•
31 May 2000
TL;DR: In this paper, a system and method for providing dynamic multimedia jitter buffer adjustment for packet-switched networks is described, where the system includes a decoder clock, a Jitter buffer, a network jitter statistics collector, and a jitter controller.
Abstract: A system and method is disclosed for providing dynamic multimedia jitter buffer adjustment for packet-switched networks. The system temporarily stores an amount of incoming data, which is dynamically adjustable, for an amount of time before sending the data out in a more even stream. The system includes a decoder clock, a jitter buffer, a network jitter statistics collector, and a jitter buffer controller. The decoder clock indicates the arrival-time of the data at the system, while the network jitter statistics collector collects the playback-time of that data. By comparing the arrival-time and the playback-time, the jitter buffer controller determines whether the data arrived on schedule. Accordingly, the depth of the jitter buffer can be adjusted to accommodate the late or early arriving data.
149 citations
Related Topics (5)
Performance Metrics
| Year | Papers |
|---|---|
| 2020 | 1 |
| 2019 | 4 |
| 2018 | 7 |
| 2017 | 9 |
| 2016 | 11 |
| 2015 | 29 |