Boolean function

Abstract: A novel method is presented for verifying functionality in the design of VLSI circuits. The method fits naturally in a methodology based on a hardware description language (HDL). Two programs describe the system under design: (1) its specification and (2) the extracted behavior from its layout. Verifying the design comes down to proving that these programs are correct and equivalent with regard to the HDL semantics. The authors define a process named formal analysis that permits to prove these properties without setting values to the programs inputs. Formal analysis is based on a canonical form of Boolean logic that is named typed Shannon's canonical form. They implemented this method in PRIAM, an efficient circuit prover now used by industrial CPU designers. >

Abstract: The controllability of probabilistic Boolean control networks (PBCNs) is first considered. Using the input-state incidence matrices of all models, we propose a reachability matrix to characterize the joint reachability. Then we prove that the joint reachability and the controllability of PBCNs are equivalent, which leads to a necessary and sufficient condition of the controllability. Then, the result of controllability is used to investigate the stability of probabilistic Boolean networks (PBNs) and the stabilization of PBCNs. A necessary and sufficient condition for the stability of PBNs is obtained first. By introducing the control-fixed point of Boolean control networks (BCNs), the stability condition has finally been developed into a necessary and sufficient condition of the stabilization of PBCNs. Both necessary and sufficient conditions for controllability and stabilizability are based on reachability matrix, which are easily computable. Hence the two necessary and sufficient conditions are straightforward verifiable. Numerical examples are provided from case to case to demonstrate the corresponding theoretical results.

Abstract: Since their introduction in the reliability field, binary decision diagrams have proved to be the most efficient tool to assess Boolean models such as fault trees. Their success increases the need of sound mathematical foundations for the notions that are involved in reliability and dependability studies. This paper clarifies the mathematical status of the notion of minimal cutsets which have a central role in fault-tree assessment. Algorithmic issues are discussed. Minimal cutsets are distinct from prime implicants and they have a great interest from both a computation complexity and practical viewpoint. Implementation of BDD algorithms is explained. All of these algorithms are implemented in the Aralia software, which is widely used. These algorithms and their mathematical foundations were designed to assess efficiently a very large noncoherent fault tree that models the emergency shutdown system of a nuclear reactor.

Abstract: We reformulate quantum query complexity in terms of inequalities and equations for a set of positive semidefinite matrices. Using the new formulation we: 1) show that the workspace of a quantum computer can be limited to at most n+k qubits (where n and k are the number of input and output bits respectively) without reducing the computational power of the model; 2) give an algorithm that on input the truth table of a partial Boolean function and an integer t runs in time polynomial in the size of the truth table and estimates, to any desired accuracy, the minimum probability of error that can be attained by a quantum query algorithm attempts to evaluate f in t queries; 3) use semidefinite programming duality to formulate a dual SDP P/spl circ/(f, t, /spl epsi/) that is feasible if and only if f cannot be evaluated within error /spl epsi/ by a t-step quantum query algorithm. Using this SDP, we derive a general lower bound for quantum query complexity that encompasses a lower bound method of Ambainis and its generalizations; 4) give an interpretation of a generalized form of branching in quantum computation.