Boolean function

Abstract: (NOTE: Each chapter ends with a summary, problems and further readings.) 1. Introduction. Design representation. Levels of abstraction. Design process. CAD tools. Typical design process. Road map. 2. Data Types and Representations. Positional number systems. Octal and hexadecimal numbers. Number system conversions. Addition and subtraction of binary numbers. Representation of negative numbers. Two's-complement addition and subtraction. Binary ultiplication. Binary division. Floating-point number representation. Binary codes for decimal numbers. Character codes. Codes for error detection and correction. Hamming codes. 3. Boolean Algebra and Logic Design. Algebraic properties. Axiomatic definition of boolean algebra. Basic theorems of boolean algebra. Boolean functions. Canonical forms. Standard forms. Digital logic gates. Extension to multiple inputs and multiple operators. Gate implementations. VLSI technology. 4. Simplification of Boolean Functions. The map representation. The map method of simplification. Don't-care conditions. The tabulation method. Technology mapping for gate arrays. Technology mapping for custom libraries. Hazard-free design. 5. Combinatorial Components. Carry-ripple adders. Carry-look-ahead adders. Adders/subtractors. Logic unit. Arithmetic-Logic Unit. Decoders. Selectors. Buses. Priority encoders. Magnitude comparators. Shifters and rotators. Read-Only memories. Programmable logic arrays. 6. Sequential Logic. SR-latch. Gated SR-latch. Gated D-latch. Flip-flops. Flip-flop types. Analysis of sequential logic. Finite-state-machine model. Synthesis of sequential logic. FSM model capture. State minimization. State encoding. Choice of memory elements. Optimization and timing. 7. Storage Components. Registers. Shift registers. Counters. BCD counter. Asynchronous counter. Register files. Random-access memories (RAMs). Push-down stacks. Firs- in-first-out queue. Simple datapaths. General datapaths. Control unit design. 8. Register-Transfer Design. Design model. FSMD definition. Algorithmic-state-machine charts. Synthesis from ASM charts. Register sharing (variable merging). Functional unit sharing (operator sharing). Bus sharing (connection merging). Register merging. Chaining and multicycling. Functional unit pipelining. ASM pipelining. Control- pipelining. Scheduling. 9. Processor Design. Instruction sets. Addressing modes. Processor design. Instruction set design. Processor design. Reduced instruction set. RISC Design. Data forwarding. Branch prediction.

Abstract: We show that there is a combinational (acyclic) Boolean circuit of complexity 0(slog s), that can be made to compute any Boolean function of complexity s by setting its specially designated set of control inputs to appropriate fixed values. We investigate the construction of such “universal circuits” further so as to exhibit directions in which refinements of the asymptotic multiplicative constant factor in the complexity bound can be found. In this pursuit useful detailed guidance is provided by available lower bound arguments. In the final section we discuss some other problems in computational complexity that can be related directly to the graph-theoretic ideas behind our constructions. For motivation we start by illustrating some of the applications of universal circuits themselves.