Abstract: We study a corpus of particular Boolean functions: the idempotents. They enable us to construct functions which achieve the best possible tradeoffs between the cryptographic fundamental properties: balancedness, correlation-immunity, a high degree and a high nonlinearity (that is a high distance from the affine functions). They all represent extremely secure cryptographic primitives to be implemented in stream ciphers.

Abstract: Advances in the design of Boolean functions using heuristic techniques are reported. A genetic algorithm capable of generating highly nonlinear balanced Boolean functions is presented. Hill climbing techniques are adapted to locate balanced, highly nonlinear Boolean functions that also almost satisfy correlation immunity. The definitions for some cryptographic properties are generalised, providing a measure suitable for use as a fitness function in a genetic algorithm seeking balanced Boolean functions that satisfy both correlation immunity and the strict avalanche criterion. Results are presented demonstrating the effectiveness of the methods.

Abstract: Guaranteeing or even estimating the routability of a portion of a placed field programmable gate array (FPGA) remains difficult or impossible in most practical applications. In this paper, we develop a novel formulation of both routing and routability estimation that relies on a rendering of the routing constraints as a single large Boolean equation. Any satisfying assignment to this equation specifies a complete detailed routing. By representing the equation as a binary decision diagram (BDD), we represent all possible routes for all nets simultaneously. Routability estimation is transformed to Boolean satisfiability, which is trivial for BDD's. We use the technique in the context of a perfect routability estimator for a global router. Experimental results from a standard FPGA benchmark suite suggest the technique is feasible for realistic circuits, but refinements are needed for very large designs.

Abstract: In this paper we show how Boolean genetic networks could be used to address complex problems in cancer biology. First, we describe a general strategy to generate Boolean genetic networks that incorporate all relevant biochemical and physiological parameters and cover all of their regulatory interactions in a deterministic manner. Second, we introduce 'realistic Boolean genetic networks' that produce time series measurements very similar to those detected in actual biological systems. Third, we outline a series of essential questions related to cancer biology and cancer therapy that could be addressed by the use of 'realistic Boolean genetic network' modeling.

Abstract: This paper describes and evaluates methods for implementing formula-specific Boolean satisfiability (SAT) solver circuits in configurable hardware. Starting from a general template design, our approach automatically generates VHDL for a circuit that is specific to the particular Boolean formula being solved. Such an approach tightly customizes the circuit to a particular problem instance. Thus, it represents an ideal use for dynamically-reconfigurable hardware, since it would be impractical to fabricate an ASIC for each Boolean formula being solved. Our approach also takes advantage of direct gate mappings and large degrees of fine-grained parallelism in the algorithm's Boolean logic evaluations. We compile our designs to two hardware targets: an IKOS logic emulation system, and Digital SRC's Pamette configurable computing board. Performance evaluations on the DIMACS SAT benchmark suite indicate that our approach offers speedups from 17X to more than a thousand times. Overall, this SAT solver demonstrates promising performance speedups on an important and complex problem with extensive applications in the CAD and AI communities.

Abstract: Given a positive Boolean function fand a subset δ of its variables, we give a combinatorial condition characterizing the existence of a prime implicant Dˆof the Boolean dual f d of f having the property that every variable in δ appears in Dˆ We show that the recognition of this property is an NP-complete problem, suggesting an inherent computational difficulty of Boolean dualization, independently of the size of the dual function. Finally it is shown that if the cardinality of δ is bounded by a constant, then the above recognition problem is polynomial. In particular, it follows that the co-ocurrence graph of the dual of a positive Boolean function can be always generated in time polynomial in the size of the function.

Abstract: Efficient techniques for the manipulation of Binary Decision Diagrams (BDDs) are key to the success of formal verification tools. Recent advances in reachability analysis and model checking algorithms have emphasized the need for efficient algorithms for the approximation and decomposition of BDDs. In this paper we present a new algorithm for approximation and analyze its performance in comparison with existing techniques. We also introduce a new decomposition algorithm that produces balanced partitions. The effectiveness of our contributions is demonstrated by improved results in reachability analysis for some hard problem instances.

Abstract: Efficient hashing is a centerpiece of modern cryptography. The progress in computing technology enables us to use 64-bit machines with the promise of 128-bit machines in the near future. To exploit fully the technology for fast hashing, we need to be able to design cryptographically strong Boolean functions in many variables which can be evaluated faster using partial evaluations from the previous rounds. We introduce a new class of Boolean functions whose evaluation is especially efficient and we call them rotation symmetric. Basic cryptographic properties of rotation-symmetric functions are investigated in a broader context of symmetric functions. An algorithm for the design of rotation-symmetric functions is given and two classes of functions are examined. These classes are important from a practical point of view as their forms are short. We show that shortening of rotation-symmetric functions paradoxically leads to more expensive evaluation process.

Abstract: We consider the problem of learning monotone Boolean functions over {0, 1}/sup n/ under the uniform distribution. Specifically, given a polynomial number of uniform random samples for an unknown monotone Boolean function f, and given polynomial completing time, we would like to approximate f as well as possible. We describe a simple algorithm that we prove achieves error at most 1/2-/spl Omega/(1//spl radic/n), improving on the previous best bound of 1/2-/spl Omega/((log/sup 2/ n)/n). We also prove that no algorithm, given a polynomial number of samples, can guarantee error 1/2-/spl omega/((log n)//spl radic/n), improving on the previous best hardness bound of O(1//spl radic/n). These lower bounds hold even if the learning algorithm is allowed membership queries. Thus this paper settles to an O(log n) factor the question of the best achievable error for learning the class of monotone Boolean functions with respect to the uniform distribution.

Abstract: We obtain the first non-trivial time-space tradeoff lower bound for functions f: {0,1}/sup n//spl rarr/{0,1} on general branching programs by exhibiting a Boolean function f that requires exponential size to be computed by any branching program of length (1+/spl epsiv/)n, for some constant /spl epsiv/>0. We also give the first separation result between the syntactic and semantic read-k models for k>1 by showing that polynomial-size semantic read-twice branching programs can compute functions that require exponential size on any syntactic read-k branching program. We also show a time-space tradeoff result on the more general R-way branching program model: for any k, we give a function that requires exponential size to be computed by length kn q-way branching programs, for some q=q(k).

Abstract: The multiplicative complexity $c_{\wedge}(f)$ of a Boolean function $f$ is the minimum number of AND gates in a circuit representing $f$ which employs only AND, XOR and NOT gates. A constructive upper bound, $c_{\wedge}(f) = 2^{\frac{n}{2} + 1}-n/2 -2$, for any Boolean function $f$ on $n$ variables ($n$ even) is given. A counting argument gives a lower bound of $c_{\wedge}(f) = 2^{\frac{n}{2}} - O(n)$. Thus we have shown a separation, by an exponential factor, between worst-case Boolean complexity (which is known to be $\Theta(2^n)$) and worst-case multiplicative complexity. A construction of circuits for symmetric Boolean functions on $n$ variables, requiring less than $n + \frac{3}{2} \sqrt{n}$ AND gates, is described.

Abstract: Boolean matching tackles the problem whether a subcircuit of a boolean network can be substituted by a cell from a cell library. In previous approaches [7, 10, 8] each pair of a subcircuit and a cell is tested for NPN equivalence. This becomes very expensive if the cell library is large. In our approach the time complexity for matching a subcircuit against a library L is almost independent of the size of L. CPU time also remains small for matching a subcircuit against the huge set of functions obtained by bridging and fixing cell inputs; but the use of these functions in technology mapping is very profitable. Our method is based on a canonical representative for each NPN equivalence class. We show how this representative can be computed efficiently and how it can be used for matching a boolcan function against a set of library functions.

Abstract: S. Yamashita et al. (1996) introduced a new category for expressing the flexibility that a node can have in a multi level network. Originally presented in the context of FPGA synthesis, the paper has wider implications which were discussed by R.K. Brayton (1997). SPFDs are essentially a set of incompletely specified functions. The increased flexibility that they offer is obtained by allowing both a node to change as well as its immediate fanins. The challenge with SPFDs is: (1) to compute them in an efficient way, and (2) to use their increased flexibility in a controlled way to optimize a circuit. We provide a complete implementation of SPFDs using BDDs and apply it to the optimization of Boolean networks. Two scenarios are presented, one which trades literals for wires and the other rewires the network by replacing one fanin at a node by a new fanin. Results on benchmark circuits are very favorable.

Abstract: The function decomposition described can identify subsets of existing features and discover nongiven functions that map these subsets to a new feature, also, it can organize the existing and new features into a hierarchy. The authors demonstrate their Hierarchy Induction Tool (HINT) system on a housing loan-allocation application. Methods for switching circuit design often implicitly deal with feature transformation. Such methods construct a circuit to implement a given or partially given tabulated Boolean function. The authors' function-decomposition method can discover and construct a hierarchy of new features that one can add to the original dataset or transform into a hierarchy of less complex datasets. The method allows the decomposition to deal with nominal-feature (that is, not necessarily binary) functions.

Abstract: Petri nets are a graph-based formalism appropriate to model concurrent systems such as asynchronous circuits or network protocols. Symbolic techniques based on Binary Decision Diagrams (BDDs) have emerged as one of the strategies to overcome the state explosion problem in the analysis of systems modeled by Petri nets. The existing techniques for state encoding use a variable-per-place strategy that leads to encoding schemes with very low density. This drawback has been partially mitigated by using Zero-Suppressed BDDs, that provide a typical reduction of BDD sizes by a factor of two. This work presents novel encoding schemes for Petri nets. By using algebraic techniques to analyze the topology of the net, sets of places "structurally related" can be derived and encoded by only using a logarithmic number of Boolean variables. Such an approach allows one to drastically decrease the number of variables for state encoding and reduce memory and CPU requirements significantly.

Abstract: The size of Ordered Binary Decision Diagrams (OBDDs) is determined by the chosen variable ordering A poor choice may cause an OBDD to be too large to fit into the available memory The decision variant of the variable ordering problem is known to be NP-complete We strengthen this result by showing that there is no polynomial time approximation scheme for the variable ordering problem unless P = NP We also prove a small lower bound on the performance ratio of a polynomial time approximation algorithm under the assumption P ≠ NP

Abstract: Mathematical morphology is the analysis of signals and images in terms of shape. Much is based on simple positive Boolean functions that are used to produce filters for binary and greyscale signals and images. In a previous development, the standard operators are applied to connected sets that form maxima and minima. These are new, powerful, general tools for analysing and representing images.

Abstract: Functional decomposition is an important technique in logic synthesis, especially for the design of lookup table based FPGA architectures. We present a method for functional decomposition with a novel concept for the exploitation of don't cares thereby combining two essential goals. The minimization of the number of decomposition functions in the current decomposition step and the extraction of common subfunctions for multi-output Boolean functions. The exploitation of symmetries of Boolean functions plays an important role in our algorithm as a means to minimize the number of decomposition functions not only for the current decomposition step but also for the (recursive) decomposition algorithm as a whole. Experimental results prove the effectiveness of our approach.

Abstract: We study the complexity of learning arbitrary Boolean functions of n variables by membership queries, if at most r variables are relevant. Problems of this type have important applications in fault searching, e.g. logical circuit testing and generalized group testing. Previous literature concentrates on special classes of such Boolean functions and considers only adaptive strategies. First we give a straightforward adaptive algorithm using O(r2r log n) queries, but actually, most queries are asked nonadaptively. This leads to the problem of purely nonadaptive learning. We give a graph-theoretic characterization of nonadaptive learning families, called r-wise bipartite connected families. By the probabilistic method we show the existence of such families of size O(r2r log n + r22r). This implies that nonadaptive attribute-efficient learning is not essentially more expensive than adaptive learning. We also sketch an explicit pseudopolynomial construction, though with a slightly worse bound. It uses the common derandomization technique of small-biased k-independent sample spaces. For the special case r = 2, we get roughly 2.275 log n adaptive queries, which is fairly close to the obvious lower bound of 2 log n. For the class of monotone functions, we prove that the optimal query number O(2r + r log n) can be already achieved in O(r) stages. On the other hand, Ω(2r log n) is a lower bound on nonadaptive queries.

Abstract: This paper investigates threshold based neural networks for periodic symmetric Boolean functions and some related operations. It is shown that any n-input variable periodic symmetric Boolean function can be implemented with a feedforward linear threshold-based neural network with size of O(log n) and depth also of O(log n), both measured in terms of neurons. The maximum weight and fan-in values are in the order of O(n). Under the same assumptions on weight and fan-in values, an asymptotic bound of O(log n) for both size and depth of the network is also derived for symmetric Boolean functions that can be decomposed into a constant number of periodic symmetric Boolean subfunctions. Based on this results neural networks for serial binary addition and multiplication of n-bit operands are also proposed. It is shown that the serial addition can be computed with polynomially bounded weights and a maximum fan-in in the order of O(log n) in O(n/log n) serial cycles. Finally, it is shown that the serial multiplication can be computed in O(n) serial cycles with O(log n) size neural gate network, and with O(n log n) latches.

Abstract: Estimates are given of the number B(n, L) of distinct functions computed by propositional formulas of size L in n variables, constructed using only literals and ∧, ∨ connectives. (L is the number of occurrences of variables. L−1 is the number of binary ∧s and ∨s. B(n, L) is also the number of functions computed by two terminal series-parallel networks with L switches.) Enroute the read-once functions, which are closely related to Schroder numbers, are enumerated. Writing B(n, L)=b(n, L)L, we find that if L and β(n) go to infinity with increasing n and L≤2n/nβ(n), then b(n, L)∼cn, where c=2/(ln 4−1). Making a comparison with polynomial size Boolean circuits, this implies the following. For any constant α>1, almost all Boolean functions with formula complexity at most nα cannot be computed by any circuit constructed from literals and fewer than α−1nα two-input ∧, ∨ gates. © 1998 John Wiley & Sons, Inc. Random Struct. Alg., 13: 349–382, 1998

Abstract: This paper addresses the problem of binary decision diagram (BDD) minimization in the presence of don't care sets. Specifically given an incompletely specified function g and a fixed ordering of the variables, we propose an exact algorithm for selecting f such that f is a cover for g and the binary decision diagram for f is of minimum size. The approach described is the only known exact algorithm for this problem not based on the enumeration of the assignments to the points in the don't care set. We show also that our problem is NP-complete. We show that the BDD minimization problem can be formulated as a binate covering problem and solved using implicit enumeration techniques. In particular, we show that the minimum-sized binary decision diagram compatible with the specification can be found by solving a problem that is very similar to the problem of reducing incompletely specified finite state machines. We report experiments of an implicit implementation of our algorithm, by means of which a class of interesting examples was solved exactly. We compare it with existing heuristic algorithms to measure the quality of the latter.

Abstract: A theorem of Markov precisely determines the number r of NEGATION gates necessary and sufficient to compute a system of boolean functions F. For a system of boolean functions on n variables, $r\leq b(n)=\lceil\log_2(n+1)\rceil$. We call a circuit using b(n) NEGATION gates negation-limited. We continue recent investigations into negation-limited circuit complexity, giving both upper and lower bounds. A circuit with inputs x1,..., xn and outputs $ eg x_1, \ldots, eg x_n$ is called an inverter, for which $r=\lceil\log_2(n+1)\rceil$. Fischer has constructed negation-limited inverters of size O(n2 log n) and depth O(log n). Recently, Tanaka and Nishino have reduced the circuit size to O(n log2 n) at the expense of increasing the depth to log2 n. We construct negation-limited inverters of size O(n log n), with depth only O(log n), and we conjecture that this is optimal. We also improve a technique of Valiant for constructing monotone circuits for slice functions (introduced by Berkowitz). Next, we introduce some lower bound techniques for negation-limited circuits. We provide a 5n+3 log(n+1)-c lower bound for the size of a negation-limited inverter. In addition, we show that for two different restricted classes of circuit, negation-limited inverters require superlinear size.

Abstract: This paper shows how genetic programming (GP) can help in nding generalizing Boolean functions when only a small part of the function values are given. The selection pressure favours functions having as few subfunctions as possible while only using essential variables, so the resulting functions should have good generalization properties. For e ciency no S-expressions are used for representation, but a special case of directed acyclic graphs known as ordered binary decision diagrams (OBDDs), making it possible to learn the 20-multiplexer.

Abstract: We determine those Boolean functions on GF(2)n which satisfy the propagation criterion of degree l and order k ≥ n − l }- 2. All of theses functions are quadratic. We design nonquadratic Boolean functions satisfying the criterion PC(l) of order k by using the Maiorana-McFarland construction involving nonlinear mappings derived from non-linear codes.

Abstract: The demand for implementing arbitrary N-variable logic functions on perceptron-like structures arises quite often in practice. It is well known, that only the linearly separable class of Boolean functions can be implemented in a single step on these structures. This class however, constitutes only a small (and with the increasing N exponentially decreasing) part of all logic functions. All Boolean functions can be trivially decomposed into at most 2N−1 sub-functions by implementing the minterm or maxterm formulation of the function. This approach, however, becomes rather impractical with the increasing number of variables. In this paper an algorithm is proposed for decomposing arbitrary, linearly non-separable Boolean functions into a series of separable functions, which can be then efficiently implemented as a program for the CNN Universal Machine assuming the simplest and most robust hardware architecture. The decomposition is achieved by finding the closest linearly separable compact functions. Robustness issues of the implementation are also addressed. © 1998 John Wiley & Sons, Ltd.