Abstract: CNN is an acronym for either Cellular Neural Network when used in the context of brain science, or Cellular Nonlinear Network when used in the context of coupled dynamical systems. A CNN is defined by two mathematical constructs: 1. A spatially discrete collection of continuous nonlinear dynamical systems called cells, where information can be encrypted into each cell via three independent variables called input, threshold, and initial state. 2. A coupling law relating one or more relevant variables of each cell Cij to all neighbor cells Ckl located within a prescribed sphere of influence Sij(r) of radius r, centered at Cij. In the special case where the CNN consists of a homogeneous array, and where its cells have no inputs, no thresholds, and no outputs, and where the sphere of influence extends only to the nearest neighbors (i.e. r = 1), the CNN reduces to the familiar concept of a nonlinear lattice. The bulk of this three-part exposition is devoted to the standard CNN equation where xij, yij, uij and zij are scalars called state, output, input, and threshold of cell Cij; akl and bkl are scalars called synaptic weights, and Sij(r) is the sphere of influence of radius r. In the special case where r = 1, a standard CNN is uniquely defined by a string of "19" real numbers (a uniform thresholdzkl = z, nine feedback synaptic weights akl, and nine control synaptic weights bkl) called a CNN gene because it completely determines the properties of the CNN. The universe of all CNN genes is called the CNN genome. Many applications from image processing, pattern recognition, and brain science can be easily implemented by a CNN "program" defined by a string of CNN genes called a CNN chromosome. The first new result presented in this exposition asserts that every Boolean function of the neighboring-cell inputs can be explicitly synthesized by a CNN chromosome. This general theorem implies that every cellular automata (with binary states) is a CNN chromosome. In particular, a constructive proof is given which shows that the game-of-life cellular automata can be realized by a CNN chromosome made of only three CNN genes. Consequently, this "game-of-life" CNN chromosome is a universal Turing machine, and is capable of self-replication in the Von Neumann sense [Berlekamp et al., 1982]. One of the new concepts presented in this exposition is that of a generalized cellular automata (GCA), which is outside the framework of classic cellular (Von Neumann) automata because it cannot be defined by local rules: It is simply defined by iterating a CNN gene, or chromosome, in a "CNN DO LOOP". This new class of generalized cellular automata includes not only global Boolean maps, but also continuum-state cellular automata where the initial state configuration and its iterates are real numbers, not just a finite number of states as in classical (von Neumann) cellular automata. Another new result reported in this exposition is the successful implementation of an analog input analog output CNN universal machine, called a CNN universal chip, on a single silicon chip. This chip is a complete dynamic array stored-program computer where a CNN chromosome (i.e. a CNN algorithm or flow chart) can be programmed and executed on the chip at an extremely high speed of 1 Tera (1012) analog instructions per second (based on a 100 × 100 chip). The CNN universal chip is based entirely on nonlinear dynamics and therefore differs from a digital computer in its fundamental operating principles. Part II of this exposition is devoted to the important subclass of autonomous CNNs where the cells have no inputs. This class of CNNs can exhibit a great variety of complex phenomena, including pattern formation, Turing patterns, knots, auto waves, spiral waves, scroll waves, and spatiotemporal chaos. It provides a unified paradigm for complexity, as well as an alternative paradigm for simulating nonlinear partial differential equations (PDE's). In this context, rather than regarding the autonomous CNN as an approximation of nonlinear PDE's, we advocate the more provocative point of view that nonlinear PDE's are merely idealizations of CNNs, because while nonlinear PDE's can be regarded as a limiting form of autonomous CNNs, only a small class of CNNs has a limiting PDE representation. Part III of this exposition is rather short but no less significant. It contains in fact the potentially most important original results of this exposition. In particular, it asserts that all of the phenomena described in the complexity literature under various names and headings (e.g. synergetics, dissipative structures, self-organization, cooperative and competitive phenomena, far-from-thermodynamic equilibrium phenomena, edge of chaos, etc.) are merely qualitative manifestations of a more fundamental and quantitative principle called the local activity dogma. It is quantitative in the sense that it not only has a precise definition but can also be explicitly tested by computing whether a certain explicitly defined expression derived from the CNN paradigm can assume a negative value or not. Stated in words, the local activity dogma asserts that in order for a system or model to exhibit any form of complexity, such as those cited above, the associated CNN parameters must be chosen so that either the cells or their couplings are locally active.

Abstract: This paper addresses the problem of computing the area complexity of a multi-output combinational logic circuit, given only its functional description, i.e., Boolean equations, where area complexity is measured in terms of the number of gates required for an optimal multilevel implementation of the combinational logic. The proposed area model is based on transforming the given, multi-output Boolean function description into an equivalent single-output function. The model, is empirical, and results demonstrating its feasibility and utility are presented. Also, a methodology for converting the gate count estimates, obtained from the area model, into capacitance estimates is presented. High-level power estimates based on the total capacitance estimates and average activity estimates are also presented.

Abstract: This paper presents a new data structure called Boolean Expression Diagrams (BEDs) for representing and manipulating Boolean functions. BEDs are a generalization of Binary Decision Diagrams (BDDs) which can represent any Boolean circuit in linear space and still maintain many of the desirable properties of BDDs. Two algorithms are described for transforming a BED into a reduced ordered BDD. One closely mimics the BDD apply-operator while the other can exploit the structural information of the Boolean expression. The efficacy of the BED representation is demonstrated by verifying that the redundant and non-redundant versions of the ISCAS 85 benchmark circuits are identical. In particular, it is verified that the two 16-bit multiplication circuits (c6288 and c6288nr) implement the same Boolean functions. Using BEDs, this verification problem is solved in less than a second, while using standard BDD techniques this problem is infeasible. BEDs are useful in applications where the end-result as a reduced ordered BDD is small, for example for tautology checking.

Abstract: We propose algorithms which combine simulation with symbolic methods for the verification of invariants. The motivation is two-fold. First, there are designs which are too complex to be formally verified using symbolic methods; however the use of symbolic techniques in conjunction with traditional simulation results in better “coverage” relative to the computational resources used. Additionally, even on designs which can be symbolically verified, the use of a hybrid methodology often detects the presence of bugs faster than either formal verification or simulation.

Abstract: In this paper, we present a new method to characterize completely specified Boolean functions. The central theme of the classification is the functional equivalence (a.k.a. Boolean matching). Two Boolean functions are equivalent if there exists input permutation, input negation, or output negation that can transform one function to the other. We have derived a method that can efficiently identify equivalence classes of Boolean functions. The well-known canonical Fixed Polarity Reed-Muller (FPRM) forms are used as a powerful analysis tool. The necessary transformations to derive one function from the other are inherent in the FPRM representations. To identify uniquely each equivalence class, a set of well-known characteristics of Boolean functions and their variables (including linearity, symmetry, total symmetry, self-complement, and self-duality) are employed. It is shown that all the equivalence classes of four-variable functions are uniquely identified where majority of the classes have a single FPRM form as their representative. The Boolean matching has applications in technology mapping and in design of standard cell libraries.

Abstract: This paper continues the work initiated by N. Creignou (1995) and S. Khanna et al. (1997) who classify maximization problems derived from Boolean constraint satisfaction. We study the approximability of minimization problems derived thence. A problem in this framework is characterized by a collection F of "constraints" (i.e., functions f: {0,1}/sup k//spl rarr/{0,1}) and an instance of a problem is constraints drawn from F applied to specified subsets of n Boolean variables. We study the two minimization analogs of classes studied by S. Khanna et al.: in one variant, namely MIN CSP (F), the objective is to find an assignment to minimize the number of unsatisfied constraints, while in the other namely MIN ONES (F), the goal is to find a satisfying assignment with minimum number of ones. These two classes together capture an entire spectrum of important minimization problems including s-t Min Cut, vertex cover hitting set with bounded size sets, integer programs with two variables per inequality graph bipartization, clause deletion in CNF formulae, and nearest codeword. Our main result is that there exists a finite partition of the space of all constraint sets such that for any given F, the approximability of MIN CSP (F) and MIN ONES (F) is completely determined by the partition containing it. Moreover we present a compact set of rules that determines which partition contains a given family F. Our classification identifies the central elements governing the approximability of problems in these classes, by unifying a large collection algorithmic and hardness of approximation results.

Abstract: This paper investigates the minimal degree of polynomialsf∈R[x] that take exactly two values on a given range of integers {0,...n}. We show that thegap, defined asn-deg(f), isO(n 548). The maximal gap forn≤128 is 3. As an application, we obtain a bound on the Fourier degree of symmetric Boolean functions.

Abstract: A nanoelectronic implementation of Boolean logic circuits is described where logic functionality is realized through charge interactions between metallic dots self-assembled on the surface of a double-barrier resonant tunneling diode (RTD) structure. The primitive computational cell in this architecture consists of a number of dots with nearest neighbor (resistive) interconnections. Specific logic functionality is provided by appropriate rectifying connections between cells. We show how basic logic gates, leading to combinational and sequential circuits, can be realized in this architecture. Additionally, architectural issues including directionality, fault tolerance, and power dissipation are discussed. Estimates based on the current-voltage characteristics of RTD's and the capacitance and resistance values of the interdot connections indicate that static power dissipation as small as 0.1 nW/gate and switching delay as small as a few picoseconds can be expected. We also present a strategy for fabricating/synthesizing such systems using chemical self-organizing/self-assembly phenomena. The proposed synthesis procedure utilizes several chemical self-assembly techniques which have been demonstrated recently, including self-assembly of uniform arrays of close-packed metallic dots with nanometer diameters, controlled resistive linking of nearest neighbor dots with conjugated organic molecules and organic rectifiers.

Abstract: The use of Ordered Binary Decision Diagrams (OB-DDs) as a representation of Boolean functions brought essential progress in many different applications. The optimization of the OBDD-size by the choice of the variable ordering is known to be NP-hard. The known heuristics for finding an initial ordering and for reordering still have insufficient performance. Rudell's sifting is one of the most successful reordering algorithms that is application independent and can be used dynamically. In this paper, we propose a method based on some communication complexity considerations that improves the time performance of the sifting. The main idea is to restrict the reordering of variables to blocks that are determined according to readily computable OBDD-measure. Experimental comparison of the proposed block-restricted sifting with the original algorithm shows a speed-up by factor two without any loss in the final size.

Abstract: A Boolean function f satisfies PC(l) of order k if f(x) ⊕ f(x ⊕ α)is balanced for any α such that 1 ≤ W(α) ≤ l even if any k input bits are kept constant, where W(α) denotes the Hamming weight of α. This paper shows the first design method of such functions which provides deg(f) ≥ 3. More than that, we show how to design "balanced' such functions. High nonlinearity and large degree are also obtained. Further, we present balanced SAC(k) functions which achieve the maximum degree. Finally, we extend our technique to vector output Boolean functions.

Abstract: A boolean multiplier is disclosed. The boolean multiplier includes a plurality of input buffers for storing a first operand and a second operand. The multiplier also includes a first set of gates coupled to the input buffers, the first set of gates respectively combining the first operand and the second operand with Boolean function to produce logical products. The multiplier further includes a second set of gates coupled to the first set of gates, the second set of gates respectively combining the logical products with Boolean functions to produce specific product bits.

Abstract: Recent results have shown that clock-gating techniques are effective in reducing the total power consumption of sequential circuits. Unfortunately, such techniques assume the availability of the state transition graph of the target system, and rely on explicit algorithms whose complexity is polynomial in the number of states, that is, exponential in the number of state variables. This assumption poses serious limitations on the size of the circuits for which automatic gated-clock generation is feasible. In this paper we propose fully symbolic algorithms for the automatic extraction and synthesis of the clock-gating circuitry for large control-oriented sequential designs. Our techniques leverage the compact BDD-based representation of Boolean and pseudo-Boolean functions to extend the applicability of gated-clock architectures to designs implemented by synchronous networks. As a result, we can deal with circuits for which the explicit state transition graph is too large to be generated and/or manipulated. Moreover, symbolic manipulation techniques allow accurate probabilistic computations; in particular, they enable the use of non-equiprobable primary input distributions, a key step in the construction of models that match the behavior of real hardware devices with a high degree of fidelity. The results are encouraging, since power savings of up to 36% have been obtained on controllers containing up to 21 registers.

Abstract: Until recently verifying multipliers with formal methods was not feasible, even for small input word sizes. About two years ago, a new data structure, called Multiplicative Binary Moment Diagram (*BMD), was introduced for representing arithmetic functions over Boolean variables. Based on this data structure, methods were proposed by which verification of multipliers with input word sizes of up to 256 bits became feasible. Only experimental data has been provided for these verification methods until now. In this paper we give a formal proof that logic verification using *BMDs is polynomially bounded in both space and time when applied to the class of Wallace-tree like multipliers.

Abstract: We present a data structure for Boolean functions, which we call Parity-OBDDs or POBDDs, which combines the nice algorithmic properties of the well-known ordered binary decision diagrams (OBDDs) with a considerably larger descriptive power.

Abstract: Definitions of a reduct for a single object, decision class and all objects of decision table for the variable precision rough set model are introduced. The definitions have a property that the set of prime implicants of minimal disjunctive normal form of a discernibility function is equal to the set of reducts. Thus the problem of reducts maintenance in dynamically extended information systems is equivalent to the problem of discernibility function maintenance. We prove that the problem can be stated in the form of a Boolean equation: g ⋀ h = f ⋀ k, where f, h and k are given monotonic Boolean functions and g is a function to be determined in minimal disjunctive normal form. An incremental algorithm finding the solution of the above equation is proposed.

Abstract: The existence of numerous number of linearly independent (L1) transformations in GF(2) algebra finds application in the design of exclusive-or based polynomial expansions. For a chosen L1 matrix transformation, such expansion gives a canonical representation of an arbitrary completely specified logical function. In this paper, family of L1 transformations is introduced which possesses fast forward and inverse butterfly diagrams. These transforms are recursively defined and grouped into classes where consistent formulas relating forward and inverse transform matrices are obtained. The classification is further extended into various L1 transforms with horizontal and vertical permutations. The possibility of easy implementation of polynomial expansions based on classified L1 logic transformations in the form of readily available fine grain FPGAs and EPLDs is also illustrated.

Abstract: Decision trees are a very general computation model. Here the problem is to identify a Boolean function f out of a given set of Boolean functions F by asking for the value of f at adaptively chosen inputs. For classes F consisting of functions which may be obtained from one function g on n inputs by replacing arbitrary n−k inputs by given constants this problem is known as attribute-efficient learning with k essential attributes. Results on general classes of functions are known. More precise and often optimal results are presented for the cases where g is one of the functions disjunction, parity or threshold.

Abstract: Recent theoretical results for pattern classification with thresholded real-valued functions (such as support vector machines, sigmoid networks, and boosting) give bounds on misclassification probability that do not depend on the size of the classifier, and hence can be considerably smaller than the bounds that follow from the VC theory In this paper, we show that these techniques can be more widely applied, by representing other boolean functions as two-layer neural networks (thresholded convex combinations of boolean functions) For example, we show that with high probability any decision tree of depth no more than d that is consistent with m training examples has misclassification probability no more than O((1/m(Neff VCdim(U) log2 m log d))1/2), where U is the class of node decision functions, and Neff ≤ N can be thought of as the effective number of leaves (it becomes small as the distribution on the leaves induced by the training data gets far from uniform) This bound is qualitatively different from the VC bound and can be considerably smaller We use the same technique to give similar results for DNF formulae

Abstract: Up to know, the known derandomization methods have been derived assuming average-case hardness conditions. In this paper we instead present the first worst-case hardness conditions sufficient to obtain P=BPP.

Abstract: In this paper we define the Kronecker Galois field decision diagrams (KGFDDs), a generalization of Kronecker decision diagrams (KDDs) to the representation of multiple-valued (MV) functions. Starting from the multi-place decision diagrams (MDDs) and Galois field decision diagrams (GFDDs) we give a generalization that allows more compact representation with respect to the nodes needed. Based on KGFDDs we present a new method for circuit design for MV circuits. In contrast to previously presented approaches the resulting circuits have only logarithmic (instead of linear) depth.

Abstract: With the increase in the complexity of VLSI circuit design and the corresponding increase in the number of logic gates on a chip, logic design errors can frequently occur. In this paper we present an efficient approach to Design Error Detection and Correction when a small number of modifications can rectify the design. Our method is based on test vector simulation and Boolean function manipulation techniques. The proposed approach guarantees to return a solution, if such a solution exists in our modification model, in a short computational time. Experimental results show the robustness of our approach.

Abstract: We present a new theory of non-disjoint serial decomposition We also present our new decomposition tool DEMAIN The decomposition approach implemented in DEMAIN relies on: a partition-based representation of Boolean functions; and an effective balanced decomposition strategy that switches between the parallel and non-disjoint serial decomposition In consequence, we applied the non-disjoint serial decomposition and parallel decomposition for efficient synthesis of FPGA-based circuits directed towards area or delay optimisation

Abstract: In this paper, the minimization of incompletely specified multi-valued functions using functional decomposition is discussed. From the aspect of machine learning, learning samples can be implemented as minterms in multi-valued logic. The representation, can then be decomposed into smaller blocks, resulting in a reduced problem complexity. This gives induced descriptions through structuring, or feature extraction, of a learning problem. Our approach to the decomposition is based on expressing a multi-valued function (learning problem) in terms of a multi-valued decision diagram that allows the use of Don't Cares. The inclusion of Don't Cares is the emphasis for this paper since multi-valued benchmarks are characterized as having many Don't Cares.

Abstract: The main difficulty in implementing cellular automata on the Cellular Neural Network Universal Machine (CNNUM) is the need to perform arbitrary logic functions of the input neighborhood. Since the architecture computes weighted sums of this neighborhood, by using a "B-template," it is limited to threshold logic, i.e., a logical operation to be computed by a single transient must be in the class of linearly separable Boolean functions. It was shown previously how a general logic function can be implemented on the CNNUM by cascading component functions from this class-namely by the direct implementation of the minterm or maxterm formulation of the desired function. However, for functions of a 3/spl times/3 input neighborhood this method may require up to 256 stages. We propose a more efficient method for implementing general logic functions on the CNNUM and other hardwares capable of performing a threshold logic function of an input neighborhood. The class of considered component functions is a superset of the minterms and maxterms but, for purposes of searchability, ease of implementation, and robustness, a subset of the general linearly separable Boolean functions. We have formulated an algorithm that will find a sequence of weight-restricted threshold logic functions (B-templates with weights from {-1, 0, +1} and a bias) that, when cascaded together using two-input logical operations, will result in the desired Boolean function. Two examples are given to exhibit the algorithm.

Abstract: An abundance of research efforts in low power logic synthesis have so far been focused on AND/OR or NAND/NOR based logic. A typical approach is to first generate an initial multi- level AND/OR or NAND/NOR representation of a boolean function. Next, the representation is optimized in terms of power. However, there are major classes of circuits such as arithmetic functions which have sizable AND/OR representations but have very compact AND/XOR representations. For these functions AND/OR based optimization approach often yields poor results. In this paper, we put forth a paradigm for low power logic synthesis based on AND/XOR representations of boolean functions. Specifically, we propose transforming a boolean function into a Fixed Polarity Reed Muller form that allows us to efficiently synthesize XOR trees and AND trees with provably minimum switching activity. Preliminary experimental results show that we attain good power savings with negligible area overhead and often area reduction when compared to conventional AND/XOR based synthesis methods and the Berkeley SIS system.

Abstract: This paper presents a new method for multi-valued simulation of digital circuits based on calculation of Boolean derivatives on structural binary decision diagrams (SBDD) (or structural alternative graphs) A procedure for calculation of the maximum of Boolean derivative on SBDDs as the basis for multi-valued simulation is described The method is applicable for component level representations of digital circuits where as components arbitrary subcircuits (macros) instead of gates are considered No dedicated model library for representing multi-valued behaviour of components is needed Instead of dedicated multi-valued models, generic ones in the form of SBDDs are used Experimental data to demonstrate the advantages of the new approach are provided