Abstract: Binary Moment Diagrams (BMDs) provide a canonical representations for linear functions similar to the way Binary Decision Diagrams (BDDs) represent Boolean functions. Within the class of linear functions, we can embed arbitrary functions from Boolean variables to integer values. BMDs can thus model the functionality of data path circuits operating over word-level data. Many important functions, including integermultiplication, that cannot be represented efficiently at the bit level with BDDs have simple representations at the word level with BMDs. Furthermore, BMDs can represent Boolean functions with around the same complexity as BDDs. We propose a hierarchical approach to verifying arithmetic circuits, where componentmodules are first shownto implement their word-level specifications. The overall circuit functionality is then verified by composing the component functions and comparing the result to the word-level circuit specification. Multipliers with word sizes of up to 256 bits have been verified by this technique.

Abstract: Ordered Binary Decision Diagrams (OBDDs) have found widespread use in CAD applications such as formal verification, logic synthesis, and test generation. OBDDs represent Boolean functions in a form that is both canonical and compact for many practical cases. They can be generated and manipulated by efficient graph algorithms. Researchers have found that many tasks can be expressed as series of operations on Boolean functions, making them candidates for OBDD-based methods. The success of OBDDs has inspired efforts to improve their efficiency and to expand their range of applicability. Techniques have been discovered to make the representation more compact and to represent other classes of functions. This has led to improved performance on existing OBDD applications, as well as enabled new classes of problems to be solved. This paper provides an overview of the state of the art in graph-based function representations. We focus on several recent advances of particular importance for formal verification and other CAD applications.

Abstract: A general explicit construction of bent functions is described, which unifies well known constructions due to Maiorana-McFarland and Dillon as two opposite extremal cases. Within this framework we also find new ways to generate bent functions. Then it is shown how the constructed bent functions can be modified in order to obtain highly nonlinear balanced Boolean functions. Although their nonlinearity is the best known so far, it remains open whether this bound can still be improved.

Abstract: We consider in this paper the problem of identifying min T(ƒ) and max F(ƒ) of a positive (i.e., monotone) Boolean function ƒ, by using membership queries only, where min T(ƒ) (max F(ƒ)) denotes the set of minimal true vectors (maximal false vectors) of ƒ. It is shown that the existence of an incrementally polynomial algorithm for this problem is equivalent to the existence of the following algorithms, where ƒ and g are positive Boolean functions: • An incrementally polynomial algorithm to dualize ƒ; • An incrementally polynomial algorithm to self-dualize ƒ; • A polynomial algorithm to decide if ƒ and are mutually dual; • A polynomial algorithm to decide if ƒ is self-dual; • A polynomial algorithm to decide if ƒ is saturated; • A polynomial algorithm in |min (ƒ)| + |max (ƒ)| to identify min (ƒ) only. Some of these are already well known open problems in the respective fields. Other related topics, including various equivalent problems encountered in hypergraph theory and theory of coteries (used in distributed systems), are also discussed.

Abstract: We address the problem of reducing the power dissipated by synchronous sequential circuits. We target the reduction of the average switching activity of the input and output state variables by minimizing the number of bit changes during state transitions. Using a probabilistic description of the finite state machines, we propose a state assignment algorithm that minimizes the Boolean distance between the codes of the states with high transition probability. We formulate a general theoretic framework for the solution of the state assignment problem, and propose different algorithms trading off computational effort for quality. We then generalize our model to take into account the estimated area of a multilevel implementation during state assignment, in order to obtain final circuits where the total power dissipation is minimized. A heuristic algorithm has been implemented and applied to standard benchmarks, resulting in a 16% average reduction in switching activity. >

Abstract: An effective logic synthesis procedure based on parallel and serial decomposition of a Boolean function is presented in this paper. The decomposition, carried out as the very first step of the .synthesis process, is based on an original representation of the function by a set of r-partitions over the set of minterms. Two different decomposition strategies, namely serial and parallel, are exploited by striking a balance between the two ideas. The presented procedure can be applied to completely or incompletely specified, single- or multiple-output functions and is suitable for different types of FPGAs including XILINX, ACTEL and ALGOTRONIX devices. The results of the benchmark experiments presented in the paper show that, in several cases, our method produces circuits of significantly reduced complexity compared to the solutions reported in the literature.

Abstract: In this paper, monotone Boolean functions are studied using harmonic analysis on the cube. The main result is that any monotone Boolean function has most of its power spectrum on its Fourier coefficients of degree at most O(√n) under any product distribution. This is similar to a result of Linial et al. [1993], which showed that AC 0 functions have almost all of their power spectrum on the coefficients of degree, at most (log n) O(1) , under the uniform distribution. As a consequence of the main result, the following two corollaries are obtained : -For any e > 0, monotone Boolean functions are PAC learnable with error e under product distributions in time 2 O((1/e) √ n) . -Any monotone Boolean function can be approximated within error e under product distributions by a non-monotone Boolean circuit of size 2 O(1/e √ n) and depth O(1/e √n). The learning algorithm runs in time subexponential as long as the required error is Ω(1/(√n log n)). It is shown that this is tight in the sense that for any subexponential time algorithm there is a monotone Boolean function for which this algorithm cannot approximate with error better than O(1/√n). The main result is also applied to other problems in learning and complexity theory. In learning theory, several polynomial-time algorithms for learning some classes of monotone Boolean functions, such as Boolean functions with O(log 2 n/log log n) relevant variables, are presented. In complexity theory, some questions regarding monotone NP-complete problems are addressed.

Abstract: A new test generation technique for path delay faults in circuits employing scan/hold type flip-flops is presented. Reduced ordered binary decision diagrams (ROBDDs) are used to represent Boolean functions realized by all signals in the circuit, as well as to represent the constraints to be satisfied by the delay fault test. Two faults are considered for each path in the circuit. For each fault, a pair of constraint functions, corresponding to the two time frames that constitute a transition, is evaluated. If the constraint function in the second time frame is non-null, robust-hazard-free-test generation for the delay fault is attempted. A robust test thus generated belongs either to the class of fully transitional path (FTP) tests or to the class of single input transition (SIT) tests. If a robust test cannot be found, the existence of a non-robust test is checked. Boolean algebraic manipulation of the constraint functions guarantees that if neither robust nor non-robust tests exist, the fault is undetectable. In its present form the method is applicable to all circuits that are amenable to analysis using ROBDDs. An implementation of this technique is used to analyze delay fault testability of ISCAS '89 benchmark circuits. These results show that the algebraic technique is one to two orders of magnitude faster than previously reported methods based on branch-and-bound algorithms. >

Abstract: Two-level logic minimization consists in finding a minimal cost sum-of-products, i.e, disjunctive normal form, of a given Boolean function. This paper presents a new algorithm to solve this problem, and gives experimental evidences showing that it outperforms the leading minimizers of several orders of magnitude. We suspect that it may be possible to explain this improvement in performance theoretically, and hope that our empirical results will stimulate research along

Abstract: This paper presents a logic synthesis method for look-up table (LUT) based field programmable gate arrays (FPGAs). We determine functions to be mapped to LUTs by functional decomposition. We use not only disjunctive decomposition but also nondisjunctive decomposition. Furthermore, we propose a new Boolean resubstitution technique customized for an LUT network synthesis. Resubstitution is used to determine whether an existing function is useful to realize another function; thus, we can share the common function among two or more functions. The Boolean resubstitution is effectively carried out by solving a support minimization problem for an incompletely specified function. We can also handle satisfiability don't cares of an LUT network using the technique.

Abstract: This paper addresses problems that arise while checking the equivalence of two Boolean functions under arbitrary input permutations The permutation problem has several applications in the synthesis and verification of combinational logic: it arises in the technology mapping stage of logic synthesis and in logic verification A popular method to solve it is to compute a signature for each variable that helps to establish a correspondence between the variables Several researchers have suggested a wide range of signatures that have been used for this purpose However, for each choice of signature, there remain variables that cannot be uniquely identified Our research has shown that, for a given example, this set of problematic variables tends to be the same-regardless of the choice of signatures The paper investigates this problem

Abstract: We propose a new strategy for generating test cases for Boolean expressions. In the past, we reported the BOR (Boolean Operator) strategy for generating test cases for predicates which are singular: which contain only one occurrence of each constituent Boolean variable. We also reported results of the empirical studies that were carried out to study the effectiveness of the strategy, but the BOR algorithm did not work well with non-singularities: multiple occurrences of constituent Boolean variables. The solution we propose for the problem is a combination of the original BOR strategy and the MI (Meaning Impact) strategy reported elsewhere. Our approach is to divide a Boolean expression into components that do not have common variables, apply the MI strategy to non-singular components, and the BOR strategy to singular components, and then apply the BOR strategy to combine the test sets generated for all component. Our empirical results indicate that our hybrid approach produces fewer tests for a Boolean expression than the MI strategy. The fault detection capability of our proposed approach has also been found to be comparable to that of the MI strategy. Our test generation strategy can be used to improve the reliability and safety of a program.

Abstract: Data structures for Boolean functions form an essential component of design automation tools, especially in the area of logic synthesis The slate of the art data structure is the ordered binary decision diagram (OBDD), which results from general binary decision diagrams (BDDs), also called branching programs, by the application of ordering restrictions In the context of EXOR-based logic synthesis another type of decision diagram (DD), called (ordered) functional decision diagram ((O)FDD), becomes important We study the relation between (ordered, free) BDDs and FDDs Both BDDs and FDDs result from DDs by defining the represented function in different ways If the underlying DD is complete, the relation between these two types of interpretation can be described by a Boolean transformation τ This allows us to relate the FDD-size of ƒ and the BDD-size of τ(ƒ) also in the case where the corresponding DDs are free or ordered, but not (necessarily) complete We use this property to derive several results on the computational power of OFDDs and OBDDs Symmetric functions are shown to have efficient representations as OBDDs and OFDDs as well Classes of functions are given that have exponentially more concise OFDDs than OBDDs, and vice versa Finally, we determine the complexity of some standard operations if OFDDs are used for the representation of Boolean functions

Abstract: In this paper the Boolean D-poset is defined and it is showed that every subset of a Boolean D-poset is a compatible set.

Abstract: We present the concept of TBDD's which considerably enlarges the class of Boolean functions that can be efficiently manipulated in terms of OBDD's. It extends the idea of using domain transformations, which is well-known in many areas of mathematics, physics, and technical sciences, to the context of OBDD-based Boolean function manipulation in CAD: Instead of working with the OBDD-representation of a function f, TBDD's allow working with an OBDD-representation of a suited cube transformed version of f. Besides of giving some theoretical insights into the new concept, we investigate in some detail cube transformations which are based on complete types. We - show that such TBDD-representations can be derived similarly as OBDD-representations, - give evidence of the practical importance of such TBDD's by presenting very small-size TBDD-representations of the hidden weighted bit functions HWBn which were proved to have only very large OBDD-representations, and - report some promising experimental results with some ISCAS benchmark circuits including the multiplier circuit C6288.

Abstract: This paper presents a novel algorithm to estimate the signal probability and switching activity at all nodes in a combinational logic circuit under a zero-delay model without constructing global BDDs. By using Taylor expansion technique, the first-order signal correlation effects due to reconvergent fan-out nodes are taken into account. High accuracy is achieved by considering the dependency of the signal probability and switching activity on each primary input. High speed is also achieved by using the incremental approach for probability calculation. Our approach is able to handle large circuits, since it does not need to construct global BDDs for the probability calculation. The analysis of the time complexity and the experimental results show the running time of our approach to be about 100 times shorter than that of the most accurate approach previously proposed and that our approach has comparable accuracy. The error of the total power estimation is about 0.5% on average.

Abstract: We present theory and a novel, implicit algorithm for functional disjoint decomposition of multiple-output functions. While a Boolean function usually has a huge number of decomposition functions, we show that not all of them are useful for multiple-output decomposition. We therefore introduce the concept of preferable decomposition functions, which are sufficient for optimal multiple-output decomposition. We describe how to implicitly compute all preferable decomposition functions of a single-output, and how to identify all common preferable decomposition functions of a multiple-output function. Due to the implicit computation in all steps, the algorithm is very efficient. Applied to FPGA synthesis, the method combines the typically separated steps of common subfunction extraction and technology mapping. Experimental results show significant reductions in area.

Abstract: Open problems about enumerating Boolean functions of cryptographic significance are (partially) solved in this paper.

Abstract: Spectral methods for analysis and design of digital logic circuits have been proposed and developed for several years. The widespread use of these techniques has suffered due to the associated computational complexity. This paper presents a new approach for the computation of spectral coefficients with polynomial complexity. Usually, the computation of the spectral coefficients involves the evaluation of inner products of vectors of exponential length. In the new approach, it is not necessary to compute inner products, rather, each spectral coefficient is expressed in terms of a measure of correlation between two Boolean functions. This formulation coupled with compact BDD representations of the functions reduces the overall complexity. Further, some computer aided design applications are presented that can make use of the new spectrum evaluation approach. In particular, the basis for a synthesis method that allows spectral coefficients to be computed in an iterative manner is outlined. The proposed synthesis approach has the advantage that it can accommodate a wide variety of constituent gates, including XOR gates, and complex subfunctions for realizing the circuits. >

Abstract: A parallel decompositional algorithm and VLSI architecture is proposed for computation of the output of a stack filter over a single window of input samples using Fibonacci p-codes. For a subclass of positive Boolean functions, a more efficient parallel algorithm and VLSI architecture for running stack filtering is also presented. The area-time complexities of the proposed designs are estimated. >

Abstract: A formula is read-once if each variable appears on at most a single input. Previously, Angluin, Hellerstein, and Karpinski gave a polynomial time algorithm hat uses membership and equivalence queries to identify exactly read once boolean formulas over the basis {AND, OR, NOT}. In this paper we consider natural generalizations of this basis, and develop exact identification algorithms for more powerful classes of read-once formulas. We show that read-once formulas over the basis of arbitrary boolean functions of constant fan-in L (i.e., any ?: {0,1}1 ? c ? k ? {0,1}, where k is a constant) are exactly identifiable i polynomial time using membership and equivalence queries. We also show that read-once formulas over the basis of arbitrary symmetric boolean functions are exactly identifiable in polynomial time in this model. Given standard cryptographic assumptions, there is no polynomial time identification algorithm for read-twice formulas over either of these bases in the model. We further show that for any basis class B meeting certain technical conditions, any polynomial time identification algorithm for read-once formulas over B can be extended to a polynomial time identification algorithm for read-once formulas over the union of B and the arbitrary functions of constant fan-in. As a result, read-once formulas over the union of arbitrary symmetric and arbitrary constant fan-in gates are also exactly identifiable in polynomial time using membership and equivalence queries.

Abstract: We analyze the I/O-complexity of existing Ordered Binary-Decision Diagram manipulation algorithms and develop new efficient algorithms. We show that these algorithms are optimal in all realistic I/O-systems.

Abstract: A characterization of definability by positive first order formulas in terms of Fraisse-Ehrenfeucht-like games is developed. Using this characterization, an elementary, purely combinatorial, proof of the failure of Lyndon's Lemma (1959) (that every monotone first order property is expressible positively) for finite models is given. The proof implies that first order logic is a bad candidate for the role of a uniform version of positive Boolean circuits of constant depth and polynomial size. Although Lyndon's Lemma fails for finite models, same similar characterization may be established for finitely monotone properties, and we formulate a particular open problem in this direction.

Abstract: We present an algorithm allowing the rapid identification of low order nonlinear Boolean functions An extension of the method allowing the identification of good low order approximations (if they exist) is then described We discuss the application of the method to cryptanalysis of black-box cipher functions We present results indicating that the method can be expected to perform better than random search in locating good low order approximating Boolean functions An expression for the effectiveness of the attack is derived, and it is shown that highly nonlinear balanced Boolean functions constructed as modified low order bent functions are particularly vulnerable to the attack The required tradeoff in resisting both linear and quadratic approximation is also discussed

Abstract: In this paper, monotone Boolean functions are studied using harmonic analysis on the cube. The main result is that any monotone Boolean function has most of its power spectrum on its Fourier coefficients of “degree” at most O(=n) under any product distribution. This is similar to a result of Linial et al. [1993], which showed that AC functions have almost all of their power spectrum on the coefficients of degree, at most (log n), under the uniform distribution. As a consequence of the main result, the following two corollaries are obtained: —For any e . 0, monotone Boolean functions are PAC learnable with error e under product distributions in time 2O((1/e)n). —Any monotone Boolean function can be approximated within error e under product distributions by a non-monotone Boolean circuit of size 2O(1/en) and depth O(1/e =n). The learning algorithm runs in time subexponential as long as the required error is V(1/(=n log n)). It is shown that this is tight in the sense that for any subexponential time algorithm there is a monotone Boolean function for which this algorithm cannot approximate with error better than O(1/=n). The main result is also applied to other problems in learning and complexity theory. In learning theory, several polynomial-time algorithms for learning some classes of monotone Boolean functions, such as Boolean functions with O(logn/log log n) relevant variables, are presented. In complexity theory, some questions regarding monotone NP-complete problems are addressed.

Abstract: Binary Decision Diagrams (BDDs) are a representation for Boolean formulas which makes many operations, in particular tautology - checking, surprisingly efficient in important practical cases. In contrast to such custom decision procedures, the HOL theorem prover expands all proofs out to a sequence of extremely simple primitive inferences. In this paper we describe how the BDD algorithm may be adapted to comply with such strictures, helping us to understand the strengths and limitations of the HOL approach.

Abstract: Korner defined the notion of graph entropy He used it to simplify the proof of the Fredman--Komlos lower bound for the family size of perfect hash functions We use this information-theoretic notion to obtain a general method for formula size lower bounds This method can be applied to low-complexity functions for which the other known general methods do not apply