Abstract: We show that a class of deterministic lattice gases with discrete Boolean elements simulates the Navier-Stokes equation, anc can be used to design simple, massively parallel computing machines.

Abstract: Kauffman's model is a random complex automata where nodes are randomly assembled. Each node σi receives K inputs from K randomly chosen nodes and the values of σi at time t + 1 is a random Boolean function of the K inputs at time t. Numerical simulations have shown that the behaviour of this model is very different for K > 2 and K ≤ 2. It is the purpose of this work to give a simple annealed approximation which predicts K = 2 as the critical value of K. This approximation gives also quantitative predictions for distances between iterated configurations. These predictions agree rather well with the numerical simulations. A possible way of improving this annealed approximation is proposed.

Abstract: A new logic minimization algorithm is presented. It finds a minimal cover for a multiple-output boolean function expressed as a list of cubes. A directed graph is used to speed up the selection of a minimal cover. Covering cycles are partitioned and branched independently to reduce greatly the branching depth. The resulting minimized list of cubes is guaranteed to be minimal in the sense that no cover with less cubes can exist. The don't care at output is handled properly. This algorithm was implemented in C language under UNIX BSD4.2. An extensive comparison with ESPRESSO IIC shows that the new algorithm is particularly attractive for functions with less than 20 input and 20 output variables.

Abstract: To reduce the size of binary decision tree-type integrated circuit representations of boolean expressions, any boolean expression or sub-expression which is fully defined by one of its partial expressions is represented by only that one partial expression. If gate branching of the decision tree is a default case which is invoked only when both partial expressions are needed to define an expression or sub-expression. These reduced size expression trees readily map into CMOS cascade logic, thereby producing low power, reasonably compact, integrated circuit representations of boolean expressions.

Abstract: It is shown that for any slice function of n variables the monotone circuit complexity exceeds the circuit complexity over a universal basis by at most a multiplicative constant factor and an additive term of order $O(n(\log n)^2 )$.

Abstract: The S-boxes used in the DES are the major cryptographic component of the system Any structure which they possess can have far reaching implications for the security of the algorithm Structure may exist as a result of design principles intended to strengthen security Structure could also exist as a “trapdoor” for breaking the system This paper examines some properties which the S-boxes satisfy and attempts to determine a reason for such structure to exist

Abstract: We show that any Boolean function f which can be expressed in a sum-of-products form using m product terms can contain as many as 2m− 1 implicants but no more.

Abstract: This paper proposes a logic VERIFIER, which verifies the correctness of the gate-level design by comparing it with the behavioral description. An improved Boolean comparison technique, which assures the absence of errors without designer's assist, is proposed. The partitioning and the minimization techniques are effective to reduce the storage required, and indispensable to verify practical sized circuits. If the design is judged incorrect, the system analyzes the result and show the area containing errors. Experimental results have proved that the VERIFIER can detect design errors completely, and indicate them to the designers in comprehensible form.

Abstract: This paper describes the salient features of CAMP, a Computer Aided Minimization Procedure for single Boolean functions. The procedure is a divide and conquer algorithm, in which the essential prime implicants are first found, and then the best cover among the selective prime implicants are chosen. A significant feature of the algorithm is that the selection of the most suitable selective prime implicant to cover a minterm is based upon the information associated with the degree and direction of adjacency of the minterm itself. The generation of the complement of the function is not a requirement of the algorithm. The procedure has been implemented in a 250 line Fortran program. For shallow functions consisting mainly of essential prime implicants (EPI's) and a few selective prime implicants (SPI's), CAMP produces the exact or near minimal sum of product form. For dense functions consisting of a large number of interconnected cyclic SPI chains, a good minimal solution is obtained by minimizing the complementary function.

Abstract: CREW-PRAM's are a powerful model of parallel computers. Lower bounds for this model are rather general. Cook, Dwork, and Reischuk upper and lower time bounds for parallel random access machines without simultaneous writes, SIAM J. Comput. (in press) proved that the CREW-PRAM complexity of Boolean functions is bounded by log b c ( f ), where b ≈ 4.79 and c ( f ) is the critical complexity of f . This lower bound is often even tight. For a class of functions F the critical complexity c ( F ), the minimum of all c ( f ) where f ∈ F , is the best general lower bound on the critical complexity of all f ∈ F . We determine the critical complexity of the set of all nondegenerate Boolean functions and all monotone nondegenerate Boolean functions up to a small additive term. And we compute exactly the critical complexity of the class of all monotone graph properties, proving partially a conjecture of Turan (1984) .

Abstract: The past decade has seen renewed interest in non Von Neuman computation by parallel processing systems. This interest on the part of solid state physicists and others has led to models of pattern recognition and associative memory (1,2,3). In these models, it is largely the dynamical attractors which are of interest as the classes, or memories, stored in the systems. Further, the mathematical tractability of threshold systems with symmetric coupling, that is, in which each binary device “fires” if a weighted sum of excitation minus inhibition exceeds some threshold, and couplings between two binary devices are symmetrical, has focused particular attention on this subclass of automata. The marked advantage of this subclass of automata is the existence of a potential function allowing prescription of weightings on inputs to each binary device in order to choose steady state attractors with desired properties such as location in state space, and stability to perturbation (1,2,3).

Abstract: Several distinct connectionistic/neural representations capable of computing arbitrary Boolean functions are described and discussed in terms of possible tradeoffs between time, space, and expressive clarity. It is suggested that the ability of a threshold logic unit (TLU) to represent prototypical groupings has significant advantages for representing real world categories. Upper and lower bounds on the number of nodes needed for Boolean completeness are demonstrated. The necessary number of nodes is shown to increase exponentially with the number of input features, the exact rate of increase depending on the representation scheme. In addition, in non-recurrent networks, connection weights are shown to increase exponentially with a linear reduction in the number of nodes below approximately 2d. This result suggests that optimum memory efficiency may require unacceptable learning time. Finally, two possible extensions to deal with non-Boolean values are considered.

Abstract: This paper presents a new theory of self-correction in circuits, one which differs from earlier methods by being completely based upon properties of Boolean functions, thus guaranteeing the universality of the methods which have already been developed. The principal result is the construction of a self-correcting, information-nonredundant Boolean function expansion, which admits an analogue in any nontrivial control system and permits the construction of asymptotically nonredundant self-correcting circuits. The Boolean functions include a broad spectrum of special classes.

Abstract: Perceptrons are defined to be multilayered networks of fixed topology that consist of adjustable combinational nodes. These nodes are not necessarily threshold gates, and the functional flexibility is present in all the layers (not just a single node or a single layer). The resulting network implements a modifiable Boolean function. The fundamental problem addressed is thus assignment of functional responsibility in a multilayered network. The original perceptron research is reviewed and its extensiveness is demonstrated. Other existing implementations, both analog and digital, are also presented, and an implementation developed by us is discussed at length. Perceptrons are useful in applications that require a fast and modifiable implementation of Boolean functions. An important emerging application domain is presented: combinational rule-based systems. It is shown that some propositional-logic rule bases can be transformed into a pair of Boolean functions, which could be implemented with perceptrons. Next, one aspect of the responsibility assignment in multilayered systems, namely the decomposition of a Boolean function on a given perceptron, is treated in detail. The theory of decomposition of Boolean functions is applied to this problem. The solution to the decomposition problem can be obtained in a straightforward fashion if the network has no fan-out connections. In a more general case, the decomposition problem is solved with a bottom-up search algorithm. At each node a few assignments are selected by a local selection criterion and tried in sequence. A reduction step between two nodes coordinates assignments to different nodes. Finally, the requirement that the given network function be specified completely in advance is relaxed. Two approaches towards distributed learning by example in binary tree networks, taken from the literature, are reviewed, followed by our contribution. The theory of decomposition of Boolean functions is again the basic tool in this study.

Abstract: According to Kauffman’s idea [Kauffman 1970a,b, 1979], one considers an ensemble of P genes which may be found in two possible states s., labelled as 0 and 1. An overall state S of the ensemble is the set {s1, s2,…, sp}, which is an element of {0,1}p. Given a mapping of {0,l}p→{0,1}p, the iteration of this mapping defines the dynamics of any initial S. In Kauffman model si at time (t+1) is determined by the states of k genes at time t, -possibly including si itself. Therefore the dynamics is defined by the set of all gene connections and, for each gene, by the data of a Boolean function, that is by an array of 2k elements whose values are either 0 or 1 (there are \( {2^{{{2^k}}}} \) possible Boolean functions). The dynamics drives any S towards a cycle of period m (1 ⩽ m ⩽ 2p), and the problem is to find out the number and the periods of those cycles when S is varied over the various possible states. A numerical study has been performed by Kauffman for k=2 and choosing at random the set of gene connections and the P Boolean functions. It appeared that: i) The average number of cycles is of the order of \( \sqrt {P} \) ii) The average period of the cycles is also of the order of \( \sqrt {P} \). This remarkable result shows up some amazing simplicity in the dynamics of a large system and, in particular, helps one to understand how a so large number of interacting genes can produce only few cellular types.

Abstract: Cellular automata are treated as neural nets and linearized in functional space. The solution of the inverse problem is exhibited. Additive automata correspond to nets of monomial non-separable Boolean functions.

Abstract: We show that two Boolean terms which are unifiable have a most general unifier, which can be described using the terms themselves and a single unifier. Techniques for finding a single unifier are given.

Abstract: In this paper, we analyze combinational logic circuits using "fan-out constraints" to generate tests for single stuck-at faults. A method of circuit transformation is employed to explicitly derive "fan-out constraints for controllability" and "fan-out constraints for observability," which are dependent Boolean functions and Boolen difference functions, respectively, in terms of primary inputs and fan-out stems. Then, a simplified version of a test generation algorithm which uses only the fan-out constraints for controllability at internal reconvergent fan-out stems is illustrated with an example. This approach differs from earlier work in that information about the circuit is accumulated and refined as the test generation process proceeds. In this test generation algorithm, the dependencies among fan-out nodes are ordered and solved in a hierarchical fashion so that the computation time for generating tests and detecting redundant faults can be greatly reduced--especially for locally redundant or "difficult" faults.

Abstract: How large are the “gaps” in the complexity hierarchies for Boolean functions with respect to network size and formula size? A gap is a non-empty interval of integers none of which is the complexity of any Boolean function. It is shown for the most natural bases that there are no gaps at all over a broad range of values and that the largest gap anywhere is less than n.

Abstract: Detecting essential primes is important in multiple-valued logic minimization. In this paper, We present a fast algorithm that can generate all essential primes without generating a prime cover of the Boolean function. A new consensus operation called asymmetric consensus (acons) is defined. In terms of acons, we prove a necessary and sufficient condition for detecting essential primes for a Boolean function with multiple-valued inputs. The detection of essential primes can be performed by using a tautology checking algorithm. We exploit the unateness of a Boolean function to speed up tautology checking. The notion of unateness considered is more general than that has appeared in the literature.

Abstract: The calculation of test patterns for PLAs is an expensive and time consuming task if a general purpose test pattern generation programm is used. A unified treatment of faults in PLAs and a test pattern generation algorithm based on the calculation of Boolean differences is given in this paper. Calculating the difference between the Boolean functions of the faulty and the fault free circuit guarantees that a test for a given fault is found if it exists. By tayloring the algorithm to the specific structure of programmable logic arrays a powerful tool for the test pattern calculation for PLAs is obtained. An important feature of the method is the ease of incorporating different fault assumptions.

Abstract: The paper presents a technique for finding Rademacher - Walsh spectral coefficients of a boolean function. The minimum speed of this technique is twice the speed of the generally adopted method.

Abstract: There exists a variety of procedures for partitioning the set of boolean functions into equivalence classes. The most compact algebraic procedure is the self-dualized classification. An alternative non-algebraic method involves the translation of the Rademacher/Walsh spectrum of a boolean function to canonic form. Two boolean functions are in the same spectral translation class if they have the same canonic spectrum. Here, we examine the connection between self-dualized and spectral classification. In particular, we identify the sequence of spectral operations equivalent to self-dualized classification, and show that each spectral equivalence class is the union of some number of self-dualized classes. This clearly shows spectral coefficient classification to be stronger than its algebraic counterparts.