Bit stuffing

Abstract: To store N bits of M≧2 logical pages, the bits are interleaved and the interleaved bits are programmed to ┌N/M┐ memory cells, M bits per cell. Preferably, the interleaving puts the same number of bits from each logical page into each bit-page of the ┌N/M┐ cells. When the bits are read from the cells, the bits are de-interleaved. The interleaving may be deterministic or random, and may be effected by software or by dedicated hardware.

Abstract: Print enhancement circuitry to enhance the printed image produced by a laser beam printer is interposed between the character generator circuits and the laser drive circuits to modify the laser drive signals provided by the character generator circuits. Bit data representing successive lines of the bit map for a desired image are stored in a first-in first-out (FIFO) buffer. The bit pattern sample window having a central cell (bit) and a selected (arbitrary) number of neighboring bits is compared to a number of matching bit patterns or templates, each of which is associated with an error element or cell. When a logic matching network detects a match, a modification signal associated with a unique compensation cell (bit) is generated. The sample window central bit is then replaced (modified) with the unique compensation bit required by the matching template. In this manner, all bits in a desired bit map, or set of bit maps, are examined and their corresponding laser drive signals modified to compensate for the errors associated with the matched templates in a piece-wise manner.

Abstract: The present invention relates to methods, apparatuses, and systems for performing data encoding involving encoding data bits according to an outer convolutional code to produce outer encoded bits processing the outer encoded bits using an interleaver and a logical unit to produce intermediate bits, wherein the logical unit receives a first number of input bits and produces a second number of corresponding output bits, the second number being less than the first number, and wherein the logical unit takes each of the first number of input bits into account in producing the second number of output bits, encoding the intermediate bits according to an inner convolutional code to produce inner encoded bits, wherein the inner convolutional code is characterized by at least two states, and combining the data bits and the inner encoded bits to produce encoded outputs.

Abstract: This technology pertains to a data-processing device and a data processing method that make it possible to ensure good communication quality when using an LDPC code to transmit data. In group-wise interleaving, an LDPC code having a code length (N) of 16,200 bits and a code rate (r) of 10/15 or 12/15 is interleaved on a per-bit-group basis, each bit group being 360 bits long. In group-wise deinterleaving, the interleaved LDPC code is restored to the original ordering thereof. This technology can be applied, for example, to data transmission or the like using an LDPC code.