Bit manipulation

Abstract: Memory cells are programmed and read, at least M=3 data bits per cell, according to a valid nonserial physical bit ordering with reference to a logical bit ordering. The logical bit ordering is chosen to give a more even distribution of error probabilities of the bits, relative to the probability distributions of the data error and the cell state transition error, than would be provided by the physical bit ordering alone. Preferably, both bit orderings have 2 M −1 transitions. Preferably, the logical bit ordering is evenly distributed. The translation between the bit orderings is done by software or hardware.

Abstract: Ternary content addressable memories (TCAMs) have become the de facto standard in industry for fast packet classification. Unfortunately, TCAMs have limitations of small capacity, high power consumption, high heat generation, and high cost. The well-known range expansion problem exacerbates these limitations as each classifier rule typically has to be converted to multiple TCAM rules. One method for coping with these limitations is to use compression schemes to reduce the number of TCAM rules required to represent a classifier. Unfortunately, all existing compression schemes only produce prefix classifiers. Thus, they all miss the compression opportunities created by non-prefix ternary classifiers. In this paper, we propose bit weaving, the first non-prefix compression scheme. Bit weaving is based on the observation that TCAM entries that have the same decision and whose predicates differ by only one bit can be merged into one entry by replacing the bit in question with . Bit weaving consists of two new techniques, bit swapping and bit merging, to first identify and then merge such rules together. The key advantages of bit weaving are that it runs fast, it is effective, and it is composable with other TCAM optimization methods as a pre/post-processing routine. We implemented bit weaving and conducted experiments on both real-world and synthetic packet classifiers. Our experimental results show the following: 1) bit weaving is an effective standalone compression technique (it achieves an average compression ratio of 23.6%); 2) bit weaving finds compression opportunities that other methods miss. Specifically, bit weaving improves the prior TCAM optimization techniques of TCAM Razor and Topological Transformation by an average of 12.8% and 36.5%, respectively.

Abstract: An internal RISC-type instruction structure furnishes a fixed bit-length template including a plurality of defined bit fields for a plurality of operation (Op) formats. One format includes an instruction-type bit field, two source-operand bit fields and one destination-operand bit field for designating a register-to-register operation. Another format is a load-store format that includes an instruction-type bit field, an identifier of a source or destination register for the respective load or store operation, and bit fields for specifying the segment, base and index parameters of an address.

Abstract: A technique for bit synchronization and error detection of received digital data bursts in a TDM/TDMA system, such as that which will be used with low power portable digital telephony. A cyclically redundant codeword, e.g. a (161,147) codeword, is formed for transmission, using e.g. either a TDM packet or TDMA burst. The first and last bits in the codeword are then inverted to form a first set of marker bits. At a receiver, a second set of marker bits is inserted into a received word, again through inverting the first and last bits. The resulting marked word is then rotated by a pre-determined number of bits to place potentially erroneous bits at the end of this word. A multi-bit timing syndrome value is then determined and is used to access a look-up table for a value of bit slippage. The received word is advanced or retarded as specified by the bit slippage value to yield an intermediate word. The marker bits are removed from the intermediate word to yield an unmarked word for which an error syndrome value is determined. If the error syndrome value is zero, then the unmarked word is a synchronized substantially error-free codeword. If the unmarked word contains excessive bit slippage or bit errors indicated by an excessive value of the timing syndrome or a non-zero valued error syndrome, an indication is provided to ignore this word.