About: Bit-length is a research topic. Over the lifetime, 717 publications have been published within this topic receiving 10746 citations. The topic is also known as: bit width & number of bit.
TL;DR: A mapping of m symbols into 2 symbols will be shown to be (2 m)/2 or ( 2 m 1)/2 symbol correcting, depending on whether m is even or odd.
Abstract: a._) into the 2-tuple (P(0), P(a), P(a:), P(1 ); this m-tuple might be some encoded message and the corresponding 2n-tuple is to be transmitted. This mapping of m symbols into 2 symbols will be shown to be (2 m)/2 or (2 m 1)/2 symbol correcting, depending on whether m is even or odd. A natural correspondence is established between the field elements of K and certain binary sequences of length n. Under this correspondence, code E may be regarded as a mapping of binary sequences of mn bits into binary sequences of n2 bits. Thus code E can be interpreted to be a systematic multiple-error-correcting code of binary sequences.
TL;DR: Since the multiplier has a regular cellular array structure similar to an array multiplier, it is suitable for VLSI implementation and is excellent in both computation speed and regularity in layout.
Abstract: A high-speed VLSI multiplication algorithm internally using redundant binary representation is proposed. In n bit binary integer multiplication, n partial products are first generated and then added up pairwise by means of a binary tree of redundant binary adders. Since parallel addition of two n-digit redundant binary numbers can be performed in a constant time independent of n without carry propagation, n bit multiplication can be performed in a time proportional to log2 n. The computation time is almost the same as that by a multiplier with a Wallace tree, in which three partial products will be converted into two, in contrast to our two-to-one conversion, and is much shorter than that by an array multiplier for longer operands. The number of computation elements of an n bit multiplier based on the algorithm is proportional to n2. It is almost the same as those of conventional ones. Furthermore, since the multiplier has a regular cellular array structure similar to an array multiplier, it is suitable for VLSI implementation. Thus, the multiplier is excellent in both computation speed and regularity in layout. It can be implemented on a VLSI chip with an area proportional to n2 log2 n. The algorithm can be directly applied to both unsigned and 2's complement binary integer multiplication.
TL;DR: A method to solve integer polynomial equations in two variables, provided that the solution is suitably bounded, and how to find the factors of N = PQ if the authors are given the high order ((1/4) log2 N) bits of P is presented.
Abstract: We present a method to solve integer polynomial equations in two variables, provided that the solution is suitably bounded. As an application, we show how to find the factors of N = PQ if we are given the high order ((1/4) log2 N) bits of P. This compares with Rivest and Shamit's requirement of ((1/3) log2 N) bits.
TL;DR: Firm lower bounds are given to minimax measures of bits stored and bits accessed for each of four retrieval questions, and representations and algorithms for a bit-addressable machine which come within factors of two or three of attaining all four bounds at once for files of any size.
Abstract: We consider a set of static files or inventories, each consisting of the same number of entries, each entry a binary word of the same fixed length selected (with replacement) from the set of all binary sequences of that length, and the entries in each file sorted into lexical order. We also consider several retrieval questions of interest for each such file. One is to find the value of the jth entry, another to find the number of entries of value less than k.When a binary representation of such a file is stored in computer memory and an algorithm or machine which knows only the file parameters (i.e. number of entries, number of possible values per entry) accesses some of the stored bits to answer a retrieval question, the number of bits stored and the number of bits accessed per retrieval question are two cost measures for the storage and retrieval task which have been used by Minsky and Papert. Bits stored depends on the representation chosen: bits accessed also depends on the retrieval question asked and on the algorithm used.We give firm lower bounds to minimax measures of bits stored and bits accessed for each of four retrieval questions, and construct representations and algorithms for a bit-addressable machine which come within factors of two or three of attaining all four bounds at once for files of any size. All four factors approach one for large enough files.
TL;DR: In this paper, the interleaving is applied to store N bits of M≧2 logical pages, and the bits are interleaved and programmed to N/M memory cells, M bits per cell.
Abstract: To store N bits of M≧2 logical pages, the bits are interleaved and the interleaved bits are programmed to ┌N/M┐ memory cells, M bits per cell. Preferably, the interleaving puts the same number of bits from each logical page into each bit-page of the ┌N/M┐ cells. When the bits are read from the cells, the bits are de-interleaved. The interleaving may be deterministic or random, and may be effected by software or by dedicated hardware.