Bit inversion

Abstract: While Phase Change Memory (PCM) holds a great promise as a complement or even replacement of DRAM-based memory and flash-based storage, it must effectively overcome its limit on write endurance to be a reliable device for an extended period of intensive use. The limited write endurance can lead to permanent stuck-at faults after a certain number of writes, which causes some memory cells permanently stuck at either ‘0’ or ‘1’. State-of-the-art solutions apply a bit inversion technique on selected bit groups of a data block after its partitioning. The effectiveness of this approach hinges on how a data block is partitioned into bit groups. While all existing solutions can separate faults into different groups for error correction, they are inadequate on three fundamental capabilities desired for any partition scheme. First, it can maximize probability of successfully re-partitioning a block so that two faults currently in the same group are placed into two new groups. Second, it can partition a block into a small number of groups for space efficiency. Third, it should spread out faults across the groups as uniformly as possible, so that more faults can be accommodated within the same number of groups. A recovery solution with these capabilities can provide strong fault tolerance with minimal overhead. We propose Aegis, a recovery solution with a systematical partition scheme using fewer groups to accommodate more faults compared with state-of-the-art schemes. The uniqueness of Aegis's partition scheme lies on its guarantee that any two bits in the same group will not be in the same group after a re-partition. Empowered by the partition scheme, Aegis can recover significantly more faults with reduced space overhead relative to state-of-the-art solutions.

Abstract: Examples of the present invention include an electronic-memory-system component. The electronic-memory-system component includes an array of data-storage elements and an encoder that receives input data, processes the input data as a two-dimensional array of bits by carrying out two passes, in one pass subjecting a portion of each row of the two-dimensional array of bits having more than a threshold weight to a first weight-reduction operation, and, in another pass, subjecting a portion of each considered column of the two-dimensional array of bits having more than a threshold weight to a second weight-reduction operation, one of the first and second weight-reduction operations employing an antipodal mapping and the other of the first and second weight-reduction operations employing bit inversion, generates a codeword corresponding to the input data, and stores the codeword in the array of data-storage elements.

Abstract: A memory device and method for storing bits in a memory array is provided. In one preferred embodiment, a memory device is provided comprising a plurality of memory cells that are in a first digital state and can be switched to a second digital state. A plurality of bits to be stored in the memory array are provided, and if the plurality of bits comprise more bits in the second digital state than in the first digital state, the plurality of bits are inverted before being stored in the memory array. In another preferred embodiment, a memory device is provided comprising a memory array and bit inversion circuitry. In yet another preferred embodiment, a plurality of bits are inverted before being stored in a memory array if the plurality of bits comprise more bits in a non-preferred digital state than in a preferred digital state.

Abstract: The demodulator demodulates received data, the Viterbi decoder decodes the received data to a bit sequence with the Viterbi algorithm according to the soft-decision estimate generated in demodulation and at the same time appends a reliability to each bit in the bit sequence. Then, a CRC circuit determines whether any error is detected or not by executing CRC on the decoded bit sequences, and, if no error is detected, the bit sequence is output as decoded data. On the other hand, if any error is detected, bit inversion is executed in the ascending order of sums of reliability for bits to be inverted until no error is detected by the CRC circuit. For this reason, the case of error detection is decreased and the work load for computing is decreased.