Abstract: The theory of error rates for narrow-band digital FM with limiter-discriminator detection and integrate and dump postdetection filtering is considered. The goal is that of simplifying the existing theory, which has evolved primarily in the frequency domain, and requires numerical integration and differentiation of Fourier series expansions, numerical convolution, and multibit pattern averaging. A fresh approach in the time domain, within certain ranges of frequency deviation ratio, and time-bandwidth product, leads to a theory which 1) gives Simple closed form solutions for the relevant system parameters, 2) allows for arbitrary IF filtering, 3) does not require numerical integration nor differentiation of Fourier series or computer convolutions, and 4) provides greater insight into the underlying error mechanisms. The subsequent, less involved BER calculations using the new approach compare favorably with previously published results. An unexpected bonus, resulting from the analysis, is that nonlinear IF filter phase characteristics can, in many cases, be shown to be unimportant in affecting the bit error rate.

Abstract: In high bit rate data transmission systems with ARQ error control, the throughput efficiency is a function of bit error rate, block or packet size, and the effect of significant round trip delays such as may be experienced in satellite communication systems. The selective-repeat ARQ scheme is capable of providing superior throughput performance independent of round trip delay, but requires excessively large receiver buffers; as a result the inferior GoBack N procedure is commonly adopted. This paper analyzes a class of mixed-mode ARQ protocol models which incorporate a selectiverepeat mode with finite receiver buffer. The protocol models are shown to be amenable to exact throughput analysis, but do assume that the round trip delay is constant and known, blocks are of constant length, and the ACK/NAK signals are returned error free. These assumptions might create difficulties for practical implementation. However, the analytical model results highlight those aspects of ARQ protocols which affect throughput performance as round trip delays increase. The results show that it is desirable for best throughput performance in practical systems that at least the first retransmission of a block following an error should be in the selective-repeat mode to obtain superior performance over GoBack N schemes. Furthermore, alternative secondary retransmission modes are considered which ensure that reliable transmission can be achieved without receiver buffer overflow, even if the selective-repeat mode retransmissions fail. It is shown that the choice of secondary mode does not have a significant effect on the throughput efficiency but has a bearing on complexity.

Abstract: The receiver sensitivity in optical communication is improved by heterodyne and/or coherent communication schemes, as compared with an ordinary intensity-modulation/direct-detection system. This paper presents the computation of the minimum signal level for achieving a prescribed bit-error rate in various heterodyne and coherent-type optical communication systems, as functions of the information-transmission rate and mixerdiode parameters. It is shown that in long-wavelength (1.3 um ~ 1.6 urn) region, the improvement in the signal level by the heterodyne/coherent schemes is relatively high (10 dB-20 dB). improvement of the receiver sensitivity especially at the longer wavelengths, because these schemes bring forth a sensitivity close to the shot-noise limit, regardless the mixer-noise performance [1]. The improvement of the sensitivity by these schemes was first computed by Yamamoto [2], who gave the BER vs. signal-power relations for various heterodyne/coherent schemes.

Abstract: A transmission system comprises apparatus for the transmission of voice signals only, data signals only, or a combination of both voice and data signals in a multiplexed stream of eight bit time slots over a single, bidirectional digital channel for a point-to-point connection In the combined mode, the encoded voice signals, using low bit rate voice encoders, are assigned to four bit positions of the eight bit time slot; the data signals are assigned to the remaining four bits Up to two bit positions normally used for data may be used for signature bits, thereby identifying whether the multiplexed stream comprises voice signals only, data signals only, or a combination of both voice and data signals Also, a minimum of one "1" bit per eight bit time slot is thereby guaranteed

Abstract: A voice signal converting device is adapted for a digital communication network which handles digitized voice signals and data signals simultaneously or equally. A bit for discriminating whether a signal in communication is a voice signal or a data signal is applied in a digital signal channel. The voice signal converting device is connected to a digital communication path to detect the discrimination bit from the incoming signal in such a manner that when a bit group corresponding to the discrimination bit represents the voice signal, the bit group is converted into a predeterminedly correlated bit group and delivered out and when the bit group corresponding to the discrimination bit represents the data signal, this bit group is delivered out in its original form. Consequently, even when the voice signal and the data signal coexist in one communication, speech quality of the voice signal and bit integrity of the data signal can be guaran

Abstract: Multi- h phase coded signals are constant-envelope sinusoids whose phase varies in a piecewise linear manner driven by cyclically chosen slopes. The transmission of these over a Gaussian noise channel with Viterbi decoder is simulated. Decoded error events are of two types normal and long, but in either case only a few bit errors are caused; events are empirically independent, they do not propagate, and their frequency is that predicted by signal space theory. Power gain compared to MSK modulation varies from 1.5 dB at bit error rate 0.05 to 4 dB at 0.0001 .

Abstract: A modularized error correction apparatus for correcting package errors is provided by expanding an N bit single error correction, double error detection code to cover N packages of M bits each, so that the Exclusive-OR of all M bit single bit error syndromes in any given package results in a composite syndrome which is unique for each package. See FIG. 2 for the parity matrix H and the matching matrix M for the error correction code.

Abstract: An error correction device for digital data storage and transfer systems wherein data are transferred over a plurality of channels. Synchronously with the transfer of a group of data bits, a coding device forms a first correction bit for a first correction channel and a second correction bit for a second correction channel. The first correction bit is formed on the basis of a second group of data bits, the second correction bits being formed on the basis of a third group of data bits. Each data channel supplies the data of two sub-groups of data bits for this purpose. The delay operator having a length of one bit cell being represented by D, a series of directly successive bits can be represented by a polynomial in D: x0.D0 +x1.D1 +x2.D2 + . . ., in which xj (j =0, 1 . . .) represents the bit value. The quotient of the polynomials relating to the two sub-groups of a data channel is different for each data channel in order to enable correction of an arbitrary error pattern in a single data channel. When the data bits and correction bits are received, a first and a second error elimination bit are calculated from the extracted data bits by using the same algorithm. Comparison of first/second correction/elimination bit produces two error detection bits. When a given number of successive error detection bits do not indicate a discrepancy, the transfer medium is error-free. When a given configuration of discrepancies is detected, a correction vector is formed which indicates, after storage, the channel containing an error, while further error detection bits indicate the error pattern which can thus be corrected.

Abstract: A forward error correcting digital transmission system having two separate transmission channels carrying redundant information. The signal on the first channel is encoded by combining each present bit with itself delayed m bits in time. The signal on the second channel may be encoded in the same manner only with a delay of n bits in time, or left without coding, i.e., n=0, in any case m and n are unequal integers. Both first and second channels are transmitted over separate transmission paths to the receiving terminal where each is independently decoded to obtain the original binary information from each received encoded signal. If an error is introduced into one of the channels during transmission, the encoded information necessarily contains an error in the present bit and its associated m or n delayed bit. Upon detection of an error by simple bit comparisons between the two decoded channels, the present decoded bit and its associated delayed decoded bit, if any, are changed in the apropriate channel in order to correct for the error.

Abstract: A common controller in the form of a programmed digital sequencer executes a series of instructions to control multiplexing-demultiplexing overhead channel format generation, frame synchronization stuff-destuff operation and automatic channel assignment in a digital TDM multiplexer-demultiplexer combination at one communication terminal to enable multiplexing N input data signals each having a predetermined bit rate into a transmitted synchronous data stream having a predetermined fixed data format and a given bit rate greater than the sum of the predetermined bit rates and to demultiplex N output data signals each having the predetermined bit rate from a received synchronous data stream having the data format and the given bit rate, where N is an integer greater than one. The disclosed common controller can be used with synchronous input and output data signals or for asynchronous input and output data signals wherein the asynchronous input and output data signals are distributed throughout the fixed data format in the time slots thereof evenly due to the automatic channel assignment. The programmed digital sequencer includes program memory means and support logic means coupled to the memory means to supply control signals in response to a plurality of digital codes present in the program memory means for multiplexing, demultiplexing, overhead channel format generation frame synchronization, stuff-destuff control and automatic channel assignment.

Abstract: An optimum predetection Gaussian bandpass filter for differential detection of MSK is derived theoretically with numerical techniques. The optimum product of bandwidth (B) and bit duration (T) , compromising the noise reduction effect with the intersymbol interference effect, is calculated at a given bit error rate (BER). It is shown that the optimum BT product is 1.21 with 4.02 dB degradation at 10-6BER where the degradation is defined as the increase in E_{b}/N_{0} relative to ideal coherent detection of MSK.

Abstract: Partial band noise jamming can severely degrade the performance of frequency-hopped, M-ary frequency-shift keyed communciation systems. This paper illustrates the tradeoffs between channel coding, diversity, and block orthogonal (MFSK) modulation as a means of overcoming the advantage of worst case, non-adaptive (as opposed to repeat-back) partial band jamming. For ease of computation, the analysis relies on exponentially tight error bounds, and is based on a noncoherent detection metric that requires jamming state information for each hop. A more robust, less complex receiver structure which eliminates the jamming knowledge requirement is shown to degrade performance less than 2-1/2 dB. The coding tradeoffs discussed in this report are exemplified in the design of a hypothetical 32 kb/s military frequency-hopped communication link.

Abstract: A method is presented to automatically inspect the block boundaries of a reconstructed two-dimensional transform coded image, to locate blocks which are most likely to contain errors, to approximate the size and type of error in the block, and to eliminate this estimated error from the picture. This method uses redundancy in the source data to provide channel error correction. No additional channel error protection bits or changes to the transmitter are required. It can be used when channel errors are unexpected prior to reception.

Abstract: This paper considers maximum-likelihood sequence estimation (MLSE) for quadrature amplitude modulation (QAM) signaling at rates approaching several baud/Hz. In this regime, intersymbol interference and possibly cross channel coupling are the dominant transmission impairments. We derive the structure of a detector that optimally accommodates both impairments. A bit error rate performance bound is found, and the concept of an error state transition matrix is introduced to facilitate the analysis. We explore a modulation scheme wherein cross-channel coupling is intentionally introduced, and find that it improves detection efficiency. The use of MLSE may be an important consideration for power and spectrally efficient digital radio systems, either terrestrial or satellite, since rates approaching the Shannon limit may be attainable without channel coding, and frequency selective fading is handled in an optimum manner.

Abstract: In order to evaluate the fidelity of a transmission line or other test object, a pseudorandom bit pattern is fed to the input end of that test object and is compared bit by bit with the pattern exiting at its output end. Since independent transmission errors are considered particularly relevant for this evaluation, in contrast to consequential errors following an initial error within a predetermined number of bit cycles, an error pulse emitted by the bit comparator causes the blocking of further error pulses for a selected time interval. The blocking may be effected by a retriggerable monoflop of adjustable off-normal period or by a presettable down counter.

Abstract: An error correcting code mechanism for SEC-DED (16, 21) or (8, 12) code to correct data bit errors caused by alpha particle impingement into high density storage units. The data word is read into and out of a high density storage unit and generated check bits are stored in low density storage immune to alpha particle radiation. Data bits and check bits, addressed in parallel are read out to error detecting and correcting circuits to determine the existence of an error only in a data bit and correct the state of the erroneous bit. The number of check bits and required parity and checking circuitry is reduced since no error checking of check bits, presumed to always be correct because of the use of low density storage occurs.

Abstract: Incoming data in binary form is retimed, and under control of a framing clock, a first counter clocks in four bits in the first stage of a preview store; and a second counter clocks in eight bits, four bits in each of the second and third stage of the preview store. The first bit in each instance is the framing bit for the next previous frame location and the second next previous frame location so long as an in-frame condition exists, and the frame control is in synchronism with the framing bits contained in the incoming data. The current data bit is compared with the bits appearing at the output of the first and second stages of the preview store to determine if the three bits comprise a valid framing sequence for a non-winking framing sequence in which any combination of the following frame bit indications may occur-F1 F0 F0 F1-where the number following the F indicates the state of the framing bit. If they do, the counters shift the four and eight bits as noted above to establish the condition necessary for comparison with the next incoming framing bit. Although the current data bit will constantly change with the character of the data, false error indications are prevented by use of a coincident circuit with the comparator output and a delayed frame clock signal. If framing errors occur, these are passed through the coincident circuit to an error density detector. If the error rate exceeds a predetermined value, the state of the output signal from the error density detector is changed. The counters respond to this condition by stepping the stored bits through the registers of the preview store one bit at a time and, of course, a comparison is made at each step and, if a valid sequence is detected, the output of the detector is applied to the counter to halt the stepping sequence. Then the counters read in the four and eight bits of data which data is then held for comparison at the next framing bit location. If the in-frame condition obtains, this sequence is repeated at each frame bit occurrence. If not, the search mode will again exist and the stepping sequence will be repeated.

Abstract: The performance of coherent QPSK, offset QPSK, and MSK modulation systems is investigated via computer simulation for TDMA transmission over satellite channels with cascaded nonlinear elements, up- and downlink fades, intersymbol interference, adjacent channel interference, and thermal noise. Three satellite transponder concepts are considered: TWTA transponders nominally operated at their saturation power under clear sky conditions, TWTA transponders nominally operated at input overdrive, and hard-limiting transponders. The performance of these modulation techniques in terms of bit error rate versus energy per information bit over thermal noise power density E_{b}/N_{0} has been evaluated for the three system concepts as a function of various system parameters. For transponder BT products in the range of 1.5-2.0, modem filter characteristics and waveform shaping have been carefully and nearly "optimally" selected to combat adjacent channel interference, which is the major source of impairments, especially under uplink fades. It has been found that, for certain system environments, MSK and OQPSK outperform QPSK. As a byproduct of this investigation, various means to minimize the effects of adjacent channel are proposed.

Abstract: A method for monitoring the bit error rate of digital signals according to the pseudo error rate technique which includes effecting an optimal regeneration of the signal elements in a main signal path by sampling each signal element in that path, and effecting a degraded regeneration of the signal elements in a secondary path. Regeneration in the secondary signal path is carried out by sampling each signal element twice to determine its value, once a fraction of half the element period before the midpoint of the element period and once the same fraction of half the element period after the midpoint of the element period, the two sampling moments being rigidly coupled together in time, comparing the result of each of the two samplings of one element in the secondary signal path with the result of the sampling of the same element in the main signal path, and utilizing the number of disagreements occurring over a given time interval as a measure for the bit error rate in the main signal path.

Abstract: The bit-error rate (BER) of a simulated PCM-ASK heterodyne-type optical communication system was measured for the first time as a function of the received signal power, to verify experimentally the theoretical prediction. This letter describes the principle of the measurement, experimental setup, and results. The bit-error rate measured as a function of the received signal power shows a good agreement with theoretical prediction.

Abstract: The coded bit error rate (BER) performance of a satellite communications system, wherein the satellite repeater contains an arbitrary nonlinearity and the system operates in the presence of pulsed radio frequency interference (RFI), is examined. A major result is an analytic method for determining soft decision statistics of the receiver demodulator output in which pulsed RFI effects are accounted for. It is further demonstrated how this result can be analytically applied to the approximate determination of the BER at the output of the Viterbi decoder when convolutional coding is employed. Computed results specialize the nonlinearity to either a hard limiter or clipper, in conjunction with an arbitrarily specified AM/PM characteristic. Performance curves examine BER sensitivity to RFI duty cycle, form of RFI (CW or noise), and various coding/decoding conditions.

Abstract: Method and apparatus for transferring digital data in a bit stream consisting of digital data words each of which words includes data bits and a parity bit are disclosed. Except for the word parity bits, the stream is transferred without additional overhead bits such as start and stop bits employed in an asynchronous transmission data format or synchronizing characters employed in a synchronous transmission data format. Method and apparatus for locking onto the parity bit of such a bit stream are disclosed which allow for digital data transfer in this format.

Abstract: An eight-terminal tapped tee fiber distribution system was constructed using six single-mode fiber access couplers. Data transmission at a 500 Mbit/s rate was demonstrated with a maximum thruput loss of -27 dB. Transmission and coupling fraction data for the couplers is given as well as throughput loss measurements for the data bus. Predicted bus capacity with this type of coupler is up to 15 terminals at 500 Mbits/s with a bit error rate of 10-9.

Abstract: A time-division multiplexing method and device are disclosed for combining a data signal and several secondary binary signals into a train of pulses, whereby data signals can be transmitted at various bit rates in synchronous or asynchronous mode. The data signal and N secondary signals are multiplexed together using two different frames respectively termed "synchronous frame" and "asynchronous frame," depending on whether data transmission is to be performed in synchronous or asynchronous mode. The asynchronous frame comprises a frame-alignment bit having a predetermined value, a data bit, and N bits pertaining respectively to the N secondary signals. The synchronous frame is divided up into n subframes, l 1 bits in length each, where n is equal to the integer that is immediately larger than the quantity N/(l 1 -2). Length l 1 is defined by the relation l 1 =LR/DR, where LR is the fixed bit rate for the pulse train resulting from the multiplexing process and DR is the bit rate for the data signal. Each subframe includes a synchronization bit whose value is complementary to that of the frame alignment bit, a data bit, and several bits pertaining respectively to the secondary signals. In addition, the last subframe includes a frame-alignment bit. Each bit within a synchronous or an asynchronous frame is associated with a control bit which has a first predetermined value when it is associated with a synchronization bit or a frame-alignment bit, and the complementary value when it is associated with a data bit or with a bit pertaining to the secondary signals. All of the frame bits together with the associated control bits are then encoded to be simultaneously transmitted over the transmission path. The frame bits define a data channel designated A, and the control bits define another channel designated B. The bits are paired off, with each pair comprising a channel A bit and the channel B bit associated therewith, and each of these pairs is encoded for transmission over the line. The invention also provides the demultiplexing method associated with the multiplexing method. The invention further provides an interface tansmitter and an interface receiver embodying the methods described above and allowing various DTE to exchange data, control and timing signals.

Abstract: A method and apparatus for determining the parity of data bits that have been disassociated from their parity bits and regrouped by a data byte shifter/converter or like apparatus. The lack of usually available parity bit association is overcome by generating a parity bit for each of the groups, including the parity bits, formed by the disassociative procedure. The group parity bits are then logically checked by an appropriate number of exclusive OR gates to determine their overall parity. A resultant parity signal is thereby generated which accurately reflects the parity state of the original data, unless an even number of bit errors have occurred. An odd number of bit errors is detected and, if appropriate, then alarmed.

Abstract: Data synchronization apparatus for a 1500 baud computer-audio frequency magnetic tape recorder interface is disclosed. The synchronization apparatus automatically detects bit cell boundaries and synchronizes at both the bit level and the byte level even if the audio waveform as read from the tape is inverted, as is the case with some tape recorders. Synchronization is performed by converting the audio waveform into a square wave and examining the square wave for predetermined pulse patterns. If one pattern is found, the positive-going edge of the waveform is selected as the bit cell boundary. If, on the other hand, another pattern is found, negative-going edges are selected as bit cell boundaries. Synchronization is achieved on a byte level by shifting incoming data into a first-in/first-out buffer and examining the stored data for a predetermined bit pattern.

Abstract: A differential pulse code modulation (DPCM) system having adaptive quantization with forward (AQF) transmission of step-size, and second-order predictors that are adaptive and operate on the locally decoded speech signal, is proposed. For a transmission rate of 40 kbits/s, a block size of 256 speech samples, the DPCM-AQF system using the sequential gradient estimation predictor (SGEP) has segmental signal-to-noise ratio (SNR) gains of 3 and 9 dB compared to the stochastic approximation predictor (SAP) and the leaky integrator, respectively. The dynamic range of the DPCM-AQF using SGEP for an SNR of 35 dB is 30 dB, and it is insensitive to block size (<512). When transmission errors are introduced, it has a higher SNR than that achieved with the leaky integrator for bit error rates <0.08 percent.

Abstract: Data synchronization apparatus for a 1500 baud computer-audio frequency magnetic tape recorder interface is disclosed. The synchronization apparatus automatically detects bit cell boundaries and synchronizes at both the bit level and the byte level even if the audio waveform as read from the tape is inverted, as is the case with some tape recorders. Synchronization is performed by squaring the audio waveform and measuring two successive time intervals occurring between three successive positive-going transitions and subtracting the resulting measurements. If the calculated difference is less than a predetermined amount, positive-going transitions of the waveform are selected as bit cell boundaries. If, on the other hand, the calculated difference is greater than the predetermined amount, negative-going edges are selected as bit cell boundaries. Synchronization is achieved on a byte level by shifting incoming data into a first-in/first-out buffer and examining the stored data for a predetermined bit pattern.