Showing papers on "Binary operation published in 1981"
Patent•
13 Jul 1981TL;DR: In this article, a pipe line product-accumulator device is formed by construction in n-MOS dynamic logic circuits, with an inherent trigger function on the outputs of full adders/subtractors.
Abstract: A device for multiplying two binary numbers in two's-complement notation having an array for forming bit-wise partial products and a further array for successively forming the result bits therefrom. The modules of the further array form either a full adder or a full subtractor under the control of a one-bit control signal. The negative sign of the most-significant bits of the factors can thus be taken into account. Devices of this kind can be linked in order to realize multiplications with higher precision, variation of the control signal signalling that only the device to which a most significant factor bit is applied takes into account a negative sign. A pipe line product-accumulator device is formed by construction in n-MOS dynamic logic circuits, with an inherent trigger function on the outputs of full adders/subtractors.
19 citations
TL;DR: For any binary operation, four alternatives exist: (i) both commutative and associative; (ii) neither associative nor associative, (iii) commu-tative but not associative); and (iv) associative-but not commu -tative.
Abstract: For any binary operation, four alternatives exist. It could be (i) both commutative and associative; (ii) neither commutative nor associative; (iii) commutative but not associative; (iv) associative but not commutative. The basic arithmetical operations provide examples for the first two possibilities. This paper presents elementary examples for the last two possibilities. It is claimed that the study of these examples is extremely important in order to understand the logical independence of commutativity and associativity.
4 citations
Patent•
25 Feb 1981
TL;DR: In this article, a binary operator (OB) and a read-only memory (M) were proposed to carry out the addition and subtraction of decimal numbers, where the binary operator receives two binary-coded decimal digits (01, 02) and performs the bit by bit addition of these input digits, and M receives the digit (S) furnished by the preceding binary operator and which, for each digit, furnishes, on external command (C1, C2), a value (R) which is the result of the relevant operation and is expressed either in binary form
Abstract: The invention relates to a device carrying out the addition and subtraction of decimal numbers. The device comprises as many sub-units (B) as the decimal numbers comprise digits. Each of these sub-units comprises a binary operator (OB) which receives two binary-coded decimal digits (01, 02) and which performs the bit by bit addition and subtraction of these input digits, and a read-only memory (M) which receives the digit (S) furnished by the preceding binary operator (OB) and which, for each digit, furnishes, on external command (C1, C2), a value (R) which is the result of the relevant operation and is expressed either in binary form or in the form of a predefined decimal code. The device applies to the construction of a decimal operator.