Binary operation

Abstract: We develop an automated approach for designing matrix multiplication algorithms based on constructions similar to the Coppersmith-Winograd construction. Using this approach we obtain a new improved bound on the matrix multiplication exponent ω

Abstract: A rack, which is the algebraic distillation of two of the Reidemeister moves, is a set with a binary operation such that right multiplication is an automorphism. Any codimension two link has a fundamental rack which contains more information than the fundamental group. Racks provide an elegant and complete algebraic framework in which to study links and knots in 3–manifolds, and also for the 3–manifolds themselves. Racks have been studied by several previous authors and have been called a variety of names. In this first paper of a series we consolidate the algebra of racks and show that the fundamental rack is a complete invariant for irreducible framed links in a 3–manifold and for the 3–manifold itself. We give some examples of computable link invariants derived from the fundamental rack and explain the connection of the theory of racks with that of braids.

Abstract: Introduction. Preliminaries. Basic concepts. Lattices. Unary and binary operations. Fundamental algebraic results. Unique factorization. Bibliography. Table of notation. Index.

Abstract: A high-speed VLSI multiplication algorithm internally using redundant binary representation is proposed. In n bit binary integer multiplication, n partial products are first generated and then added up pairwise by means of a binary tree of redundant binary adders. Since parallel addition of two n-digit redundant binary numbers can be performed in a constant time independent of n without carry propagation, n bit multiplication can be performed in a time proportional to log2 n. The computation time is almost the same as that by a multiplier with a Wallace tree, in which three partial products will be converted into two, in contrast to our two-to-one conversion, and is much shorter than that by an array multiplier for longer operands. The number of computation elements of an n bit multiplier based on the algorithm is proportional to n2. It is almost the same as those of conventional ones. Furthermore, since the multiplier has a regular cellular array structure similar to an array multiplier, it is suitable for VLSI implementation. Thus, the multiplier is excellent in both computation speed and regularity in layout. It can be implemented on a VLSI chip with an area proportional to n2 log2 n. The algorithm can be directly applied to both unsigned and 2's complement binary integer multiplication.