Berger code

Abstract: A strongly fault secure (SFS) ALU design based on the Berger check prediction (BCP) technique is presented. The fault and error models of a large class of VLSI ALU designs are discussed. The proposed design is proved to be fault-secure and self-testing with respect to any single fault in the ALU part. The proposed BCP ALU is proved to be SFS with any design of BCP circuit. Consequently, a self-checking processor whose data path is encoded entirely in a Berger code can be achieved. An efficient self-checking processor can then be designed. >

Abstract: An N bit input word is partitioned into parts, preferably N/3 parts of 3 bits each. Each part is counted in parallel for the number of binary ones contained therein in first stage parallel code generators, preferably in N/3 parallel berger code generators each producing on 2 binary encoded signal lines that number of binary ones as are contained within 3 input signal lines. The binary encoded signal lines from the parallel code generators are added in a second stage binary tree of adders, such adders as are used in conjunction with first stage berger code generators progressing from N/6 adders of 2 bits width at level 1 to 1 adder of ln 2 (N/3)+1 bits width at level ln 2 (N/3). The final adder produces (X+1) binary encoded signals representing the number of binary ones contained within the input word, 2 X+1 ≧ N. A final comparator stage based on exclusive OR gates and an OR gate(s) compares the X+1 signals representing the actual bit count with an equal number of binary encoded signals representing the then desired number M, M≦N, and produces an error signal if the number of binary ones detected is not equal to M. A preferred embodiment implementation of the berger code generator circuits utilizes exclusive OR logical elements based on the CMOS technology transfer gate structure.

Abstract: Design of totally self-checking (TSC) checkers for separable codes is studied. Assuming a specific checker design, a sufficient condition on separable codes is derived such that the assumed checker is TSC. It is shown that the proposed checker is applicable to certain Berger codes and residue codes. A class of codes equivalent to Berger codes is derived for which the proposed checker is TSC.

Abstract: This paper proposes a new class of codes termed "weight-based codes" where each output bit is assigned a weight and the check bits represent the stem of the weights of the output bits which have value "1". A Berger code is a special member of this proposed class of codes where each output bit is assigned a weight of one. This paper describes the application of these codes for the efficient on-line error detection of arbitrary multilevel circuits. The overall probability of detecting any number of erroneous bits at the output caused by a single internal fault is shown to be higher for weight-based codes than standard error detecting codes. Further, a very efficient design exists for the checker. The checker is area and speed efficient, has low power consumption, and can be tested by a small set of incoming code words. There is always a tradeoff between the fault detection capability and area overhead requirement of an error detecting code. Weight-based codes present a controlled way of increasing the number of check bits to achieve a desired fault detection capability.