BDPC

Abstract: The Bisulfite Sequencing Data Presentation and Compilation (BDPC) web interface for compilation and presentation of data from bisulfite sequencing DNA methylation studies has been improved by adding a new module. This module allows visualization of the whole data set in form of a heatmap of DNA methylation levels and clustering and comparison of tissue methylation patterns. It can also be used for data not processed by BDPC. In addition, several functions of the existing BDPC compilation module have been improved.

Abstract: In this paper, a symmetric stepped-impedance coupled line (SSICL) is proposed to realize dual-band quarter-wave coupled line (DQCL), giving the same equivalent even and odd characteristic impedances at two different frequencies. The DQCL can be directly used to design dual-band parallel-line coupler (DBPC) with arbitrary coupling coefficient and large frequency ratio, resulting in even shorter total length when compared with traditional quarter-wave parallel-line coupler working at lower frequency $f_{1}$ . In addition, broad DBPC (BDPC) is constructed by cascading multiple sections of SSICLs, as the SSICL is quite similar with quarter-wave coupled line in circuit. For demonstrating the design methods, in the first step, two edge-coupled 20-dB DBPCs and one broadside coupled 6-dB DBPC, working at 1/5.2, 1/7.5, and 1/5.2 GHz, respectively, are designed, fabricated and measured, exhibiting good features like large frequency ratio, high isolations, and compact dimensions. Then, for broadening bandwidths, three-section BDPC working at 1 GHz/5.2 GHz is designed and measured, resulting in working bandwidths larger than 1.2 GHz. These good features have proved the feasibility of the proposed circuits and the corresponding design methods.

Abstract: Currently, the multiprocessor architecture platform becomes more and more popular to the applications with higher computational capacity for meeting the fast-grown demand of applications and increasing the performance of whole system. Managing the consumption of resources has become an important issue in many different settings. The energyefficient scheduling for multiprocessors becomes one of important research issues. In this paper we study the scheduling problem of a heterogeneous non-DVSmultiprocessor platform with a task set. The processors have different characteristics of power consumption. We propose an off-line taskto- processor assignment algorithm, the Best-Fit Decreasing Physical Power Consumption (BDPC) algorithm to derive a feasible task assignment with the minimal energy consumption and has the time complexity of O(N(logN + M)), where N and M are the numbers of tasks and processor types, respectively. A series of experiments were conducted to evaluate the proposed algorithm. The experimental results demonstrate that the performance of the proposed BDPC algorithm is better than the compared algorithms.