BCDMOS

Abstract: A piezoelectric (PE) energy harvesting system with one-cycle maximum power point (MPP) sensing is presented. The one-cycle MPP sensing method uses a very small size sensing capacitor and it can make the transducer output voltage reach the open circuit voltage within one cycle. The proposed MPP sensing block can sense the open circuit voltage with a proposed peak detector and stores the MPP voltage using charge sharing blocks. The one-cycle MPP sensing approach simplifies the design of an MPP tracking algorithm and greatly reduces the tracking time. All control blocks are self-biased and choose the higher voltage between the input or output voltages of the switching converter as a supply voltage (V $_{DD}$ ). Therefore, a voltage multiplexer and a low-power ramp generator with V $_{DD}$ independence are also proposed to control the system without additional DC to DC converter. The entire system has been implemented in a 0.35 µm BCDMOS process. It operates at 90 kHz with a 10-mH inductor. The total power dissipation of the controller is 10 µW at a V $_{DD}$ of 2.7 V. The MPP tracking time is only 9.09 ms/V when the input voltage of the switching converter is changed from 3.4 V to 1.2 V.

Abstract: A 2/spl times/40 W class D amplifier chip is realized in 0.6-/spl mu/m BCDMOS technology, integrating two delta-sigma (/spl Delta//spl Sigma/) modulators and two full H-bridge switching output stages. Analog feedback from H-bridge outputs helps achieve 67-dB power supply rejection ratio, 0.001% total harmonic distortion, and 104-dB dynamic range. The modulator clock rate is 6 MHz, but dynamically adjusted quantizer hysteresis reduces output data rate to 450 kHz, helping achieve 88% power efficiency. At AM radio frequencies, the modulator output spectrum contains a single peak, but is otherwise tone-free, unlike conventional pulse-width modulation (PWM) modulators which contain energetic tones at harmonics of the PWM clock frequency.

Abstract: An active power-factor correction (PFC) circuit is presented that employs a newly proposed resistor-free zero-current detection (ZCD). While the conventional ZCD requires either a sensing resistor or auxiliary transformer, the proposed ZCD requires only one OFF-chip capacitor. The active PFC circuit with the proposed resistor-free ZCD has been implemented in a 0.35-μm BCDMOS process and the power factor is improved up to 9% from the one employing the conventional ZCD. The proposed resistor-free ZCD scheme can be applied to any type of switch-mode dc-dc power converter.

Abstract: A quasi-resonant (QR) controller with an adaptive frequency reduction scheme has been developed for a flyback converter. While maintaining the valley switching, the QR controller reduces the switching frequency for lighter load by skipping some valleys to reduce the power loss and thereby achieve better light-load efficiency. If the QR controller cannot detect any valley due to the damped oscillation of switch voltage, then the valley switching is given up and the nonvalley switching is employed to keep reducing the switching frequency for lighter load. The proposed QR controller has been implemented in a $\text{0.35}\hbox{-}\upmu\text{m}$ 700-V BCDMOS process and applied to a 40-W flyback converter. The power efficiency of the flyback converter is improved by upto 3.0% when the proposed QR controller is employed compared to the one employing the conventional QR controller.