Abstract: High-baud-rate coherent optical system is essential to support the ever-increasing demand for high-speed applications. Owing to the recent progress in advanced modulation formats, over 1 Tb/s single-carrier data transmission has been achieved in the laboratory, and its commercial application is envisioned in the near future. This paper presented the trend of increasing baud rate and utilizing high-order quadrature-amplitude modulation (QAM), and several enabling technologies in the coherent optical communication systems. We first discussed recent progress of high-order QAM system and digital signal processing technology. Furthermore, we compared the transmission performance of three different ultrahigh-order QAM formats. The paper then reviewed the commonly used methods of achieving over 100 GBaud optically modulated signals. Besides, five attractive modulators and their corresponding modulation structures are illustrated. Key performance parameters including electrode length, 3-dB bandwidth, half-wave voltage, extinction ratio and optical loss are also compared. Finally, the trade-off between the baud rate and QAM orders in implementing high-speed systems are investigated in simulations. The results show that for the coming 800 GbE or 1.6 TbE, PDM-64-QAM might be an idea choice by considering the trade-off between the link reach and required system bandwidth. By adopting the latest probabilistic shaping technology, higher-order QAM signals, such as PS PDM-256-QAM, could be favorable for long reach applications while using extra system bandwidth.

Abstract: In this paper, a universal asynchronous receiver and transmitter (UART) are described, which is basically a serial data transmission protocol used in digital circuit applications. The architecture of the UART transmitter has a baud rate generator, parity generator, transmitter finite state machine (FSM) and parallel in serial out register (PISO). UART receiver has a baud rate generator, negative edge detector, parity checker, receiver finite state machine (FSM) and serial in parallel out (SIPO) register. The baud rate generator of both transmitter and receiver is the same, so the baud rate of transmitter/receiver is the same. Baud rate generator is the same as the frequency divider circuit. The data frame of the UART transmitter is 1 start bit, 8 transmits data bits, 1 parity bit and 1 stop bit. The baud rate of the transmitter and receiver is 4 Mbps using the system clock of 64 MHz’s. Implementation, simulation, and synthesis is done Xilinx Vivado 2016.2 version tool. The design is verified using simulated waveform and synthesized on the FPGA Zed board.

Abstract: We analyze a feasible high-sensitivity homodyne coherent optical receiver for demodulating optical quadrature phase-shift keying (QPSK). A fourth-power phase-lock loop based on a digital look-up table is used. Considering the non-negligible loop delay, we optimize the loop natural frequency. Without error correction coding, a sensitivity of −37 dBm/−35 dBm is achieved, while the bit error rate is below 10−9 at 2.5 Gbaud/5 Gbaud rate. For the QPSK communication system, the bit rate is twice the baud rate. The loop natural frequency is 0.647 Mrad/s, and the minimized steady-state phase-error standard deviation is 3.83°.

Abstract: UART is one of the most widely used interfaces. It is as single bit TX and RX interface which supports multiple configurations. It supports data length of 5–8 bits, even, odd or missing parity bit and 3 more stop bit counts. As most UART devices have fixed configuration it usually requires manual configuration of both sides to support proper data transfers. This paper presents a novel design of UART interface that will remove that limitation. Proposed UART controller can detect baud rate automatically and adjust to it. Additionally, there is a new command interface which is used to understand remaining config of the device to fully adapt to the connected device. That will allow any device to connect to proposed UART controller and work without any manual configuration. The UART controller RTL has been developed using Verilog and the test environment was developed using SystemVerilog. Simulations have been done using VCS.

Abstract: A novel timing phase detector using one sample per symbol is developed. The phase detector is especially suitable for systems suffering from serious bandwidth limitations. Its superior performance is demonstrated in simulations and experiments.

Abstract: This paper provides experimental results for a multi-user visible light communications system using multi-band carrier-less amplitude and phase (m-CAP) modulation scheme. We optimize the system performance by adapting pulse shaping filter parameters, subcarrier spacing and allocating different baud rates to individual sub-bands called allocated m-CAP (Am-CAP). We show that a maximal system data rate of ∼468 Mb/s for four users can be supported while gaining higher flexibility for optimization and the same or lower computational complexity compared with the conventional m-CAP scheme.

Abstract: In this paper, we propose fractional sampling for optical orthogonal frequency division multiplexing (O-OFDM) in order to achieve diversity gain for indoor visible light communication systems. Fractional sampling (FS) is a diversity technique that generates different replicas of the received OFDM symbol by sampling the received signal higher than the baud rate. Indoor optical wireless channels exhibit frequency selectivity and FS increases the reliability of the transmission by exploiting the multipath diversity. Our numerical results show that for a realistic indoor channel model, proposed FS receiver provides significant performance improvement over conventional OFDM receiver.

Abstract: We propose and simulate a pattern recognition system of QPSK signals for all-optical high speed optoelectronic firewalls. Arbitrary target pattern can be recognized and a baud rate of 200 GBaud can be achieved. © 2020 The Author(s)

Abstract: Coherent optical transceivers cover multiple wavelengths to meet the growing request for ultra-wideband data links, e.g. from ultra-high definition video-on-demand. However, costs increase with the number of wavelengths per channel, so that higher baud rates are used to reduce the receiver's complexity, while simultaneously increasing electrical bandwidth requirements. Especially sampling rate and analog input bandwidth between photodiode and data converters need to be improved. For that purpose, we present a 4-way time-interleaving analog demultiplexer in one of the most advanced SiGe-BiCMOS technologies to date, operating at the highest reported sampling rate of 128 GS/s. The total harmonic distortion of −37 to −22 dB indicates an accuracy of 5.9–3.3 ENOB THD across the entire 36-GHz bandwidth of the sampled signal path and the signal-to-noise ratio of 28 dB at 2 GHz enables 4.4 ENOB SNR . Each of the sampling front end's four output paths can drive a 32-GS/s 6-bit analog-to-digital converter that can be connected to commercially available 32-Gbit/s digital interfaces. Combining an ultra-high symbol rate with medium accuracy allows for a data rate beyond 1 Tbit/s per wavelength with dual polarization and quadrature amplitude modulation in a cost-efficient coherent optical receiver.

Abstract: The invention discloses an imaging synchronous control system of a multi-channel CMOS, relates to an imaging synchronous control system of the multi-channel CMOS, and solves the problem that related clocks cannot be used for control due to the 8-time non-integral multiple relationship between the frequency of a clock and the Baud rate of a serial 422 in the conventional CMOS driving time sequence.For the application of a plurality of groups of imaging controllers, the problems of difficulty in image pickup synchronization among the imaging controllers and the like exist. Each imaging group outputs an independent row period signal for synchronous control of camera shooting; the 422 serial communication control module receives a 422 command sent by the camera controller. The time sequence driving control module generates a time sequence and a driving signal which meet voltage and current requirements. The imaging focal plane module is used for carrying out photoelectric conversion and generating a voltage and a bias signal required by the detector at the same time. The data conditioning and sending module is used for conditioning the multi-channel serial data and outputting data meeting a data transmission interface protocol. The data transmission interface module outputs a signal specified by a data transmission interface protocol. According to the invention, the shooting synchronism of each group can be ensured to the greatest extent.

Abstract: We present a numerical study of probabilistic constellation shaping gains in low resolution digital to analogue converters based transceivers, which utilise digital resolution enhancement. A signal to noise ratio gain of 0.75dB for optimized probabilistic shaping factors is achievable.

Abstract: An example apparatus includes a line driver and an interface circuit. The line driver has a plurality of source-series terminated (SST) driver segments including switching circuitry to selectively switch among at least three voltage-reference levels to drive an output node, common to each of the SST driver segments, in response to received digital signals by switching at a rate that is faster than a baud rate characterizing the received digital signals. The interface circuit drives a transmission link, in response to a drive signal at the output node, with an analog signal representing an oversampling of the received digital signals.

Abstract: In-service transceiver calibration is necessary for hot pluggable modules to achieve optimal component performance, especially for high baud rate and high order modulation systems. Here, two 4 × 2 complex-valued equalizers operating at twice symbol rates are designed before and after carrier phase recovery to compensate Rx and Tx imbalance, respectively. Transceiver gain imbalance, phase imbalance and skew could be derived from the converged two equalizers taps. The proposed scheme is evaluated in a 42 GBaud PDM-16QAM system through 900-km standard single-mode fiber transmission. The experimental results show that the accuracies of gain, phase and skew measurements are greater than 0.1 dB, 0.2 deg. and 0.1 ps for the receiver, 0.2 dB, 0.4 deg. and 0.6 ps for the transmitter.

Abstract: Packet Compressed Sensing Imaging (PCSI) is digital unconnected image transmission method resilient to packet loss. The goal is to develop a robust image transmission method that is computationally trivial to transmit (e.g., compatible with low-power 8-bit microcontrollers) and well suited for weak signal environments where packets are likely to be lost. In other image transmission techniques, noise and packet loss leads to parts of the image being distorted or missing. In PCSI, every packet contains random pixel information from the entire image, and each additional packet received (in any order) simply enhances image quality. Satisfactory SSTV resolution (320x240 pixel) images can be received in ~1-2 minutes when transmitted at 1200 baud AFSK, which is on par with analog SSTV transmission time. Image transmission and reception can occur simultaneously on a computer, and multiple images can be received from multiple stations simultaneously - allowing for the creation of "image nets." This paper presents a simple computer application for Windows, Mac, and Linux that implements PCSI transmission and reception on any KISS compatible hardware or software modem on any band and digital mode.

Abstract: Relay is first line of defense of any Power Protection System. Relay send signal to circuit breaker if any abnormal activity found in system and as soon as circuit breaker detects abnormal behaviour of the system it disconnect the faulty part from the system for proper functioning of the system minimize the loss to the active system. Initially researchers implemented various relay with help of microprocessor due to flexibility and programming approach. But drawback of this approach is its speed as sequential implementation. In this paper concurrent architecture based differential relays implemented on Virtex 5 XC5VLX50T FFG1136C FPGA board. The results are communicated to UART interface. Baud rate of the serial communication can be achieved with help of clock divider circuit. The pipeline architecture of the FPGA improves speed and efficiency of the relay. Differential relay is implemented with help of VHDL programming and IP cores.

Abstract: This paper presents the packet processing and transmission of a field programmable gate array (FPGA) development board by using an RS-485 interface module and Verilog HDL. The proposed communication protocol was established between the sensors in the sensing layer and web server. In the sensing layer, the sensor system, which comprises a temperature sensor, warning light, and fan, controls the environment temperature. An attractive Internet of Things application system was proposed to simultaneously monitor real-time temperature information through wireless communication and the webpage. Node-RED software was used to develop the home care system because of its advantages in facilitating management and maintenance. The linkage function was written in the JavaScript language on Node-RED software. In the designed system, when the temperature reaches the preset value, the fan and warning light automatically turn on and a notification email is sent to the user. The measurement results showed that the throughput and conversion time were 0.00958 Mbps and 283.83 ms, respectively, at a clock frequency of 1 MHz and Baud rate of 9600 bps.

Abstract: A 20 Gb/s serial link transceiver employing a framed-pulsewidth modulation (FPWM) scheme that overcomes the signal-to-noise (SNR) degradation without a linearity requirement is presented. The FPWM scheme encodes data at the location and the width of the pulses in a frame spanning multiple unit intervals (UI) while maintaining a minimum pulsewidth equal to 1 UI. The test chip achieves a coding gain of 33 %, which allows a total throughput of 20 Gb/s while keeping the baud rate of 15 Gb/s. The equalization core incorporating programmable 3-tap pre-emphasis at the transmitter and a continuous-time linear equalizer (CTLE) at the receiver compensates for the channel insertion loss up to 12 dB at the baud frequency, and achieves $2.2\times0.48$ mm 2 and consumes 90.6 mW from a 0.9 V supply which renders the power efficiency of 4.53 mW/Gb/s.

Abstract: A simple and inexpensive system capable of displaying relevant power quality data of a residential voltage signal is presented, and it is based on Arduino, Python and Kivy. A circuit for adjusting the voltage signal for sampling is suggested. The software of the system allows the transmission of data with any device capable of serial communication at a 2000000 Baud rate, although an Arduino NANO/UNO board is recommended A board based on an Arduino NANO R3 was used. The software plots the last 6 cycles contained in the data by default, but lets analyze any amount of cycles. It provides the RMS voltage, the peak voltage and the total harmonic distortion of the scrutinized cycles, up to the 25th harmonic. The software is also capable of calculating the fast Fourier transform of the studied cycles, and returning the corresponding plot. A sample of data captured at Maracaibo, Venezuela is shown.

Abstract: A reception device 20 is configured to include a separation means 21 and a plurality of optical reception means 22. Each optical reception means 22 further includes an optical/electrical conversion means 23, a reception coefficient computation means 24, and a band restoration means 25. The separation means 21 separates a multiplexed signal into which signals of respective channels to which spectral shaping that narrows bandwidth to less than or equal to a baud rate is applied as band narrowing filter processing on the transmission side, based on characteristics of a transmission line are multiplexed at spacings less than or equal to the baud rate. Each band restoration means 25 applies processing having inverse characteristics to those of the band narrowing filter processing to a reception signal, based on the band narrowing parameter acquired by the reception coefficient computation means 24 and thereby restores the band of the reception signal.

Abstract: We report the influence of carrier phase recovery on the subcarrier baud that minimizes Kerr-related nonlinear noise.

Abstract: In this chapter, we introduce and analyze the coherent optical transmission systemWe focus on the quasi-linear coherent optical detection system based on advanced digital signal processing technology, including front-end linear pre-equalization algorithm and back-end nonlinear processing algorithm The bandwidth limitations of the device and the nonlinear damage of the fiber link have always been two important factors limiting the transmission of high-speed optical signals The former limits the bandwidth and baud rate of the signal generation, while the latter limits the transmission distance of high-speed signals

Abstract: A baud rate calibration circuit and a serial chip. The calibration circuit comprises: a first counter (101) connected with a receiving module (20) of a serial chip, wherein the first counter is used for recording a first low-level duration of a data frame received by the receiving module; a second counter (102) connected with the receiving module, wherein the second counter is used for receiving a bit sampling pulse and recording the number of bit sampling pulses within the first low-level duration, and the bit sampling pulse is generated by the receiving module sampling the data frame according to the current baud rate of the receiving module; a divider (103) connected with the first counter and the second counter, wherein the divider is used for calculating a calibration baud rate according to the first low-level duration and the number of bit sampling pulses within the first low-level duration; and a selector (104) connected with the receiving module and the divider, wherein the selector is used for outputting the calibration baud rate to the receiving module. The present solution may realize the dynamic real-time calibration of the baud rate and improve the reliability of data reception.

Abstract: In this study, a field-programmable gate array (FPGA) based high rate transmitter is developed for low earth orbit satellite communication links using adaptive coding and modulation (ACM) techniques. The developed transmitter structure is modeled in MATLAB. Then, the MATLAB model is taken as reference for developing an FPGA design. This design is implemented on Xilinx Kintex Ultrascale XCKU060 FPGA which provides high performance and whose space grade model will be on product line in December 2020. It is shown that the developed transmitter structure can reach a spectral efficiency of 7.068 bits per second per Hertz (bps/Hz) with a code rate of 0.8889 in the highest rate mode. The implemented FPGA design of the transmitter structure can support input data rates from 50.7225 megabits per second (Mbps) to 530.1 Mbps with a baud rate of 75 mega symbol per second (Msps) and a sampling rate of 300 mega sample per second (MSps) at the output.

Abstract: The present disclosure relates to a circuit for calibrating a baud rate. The circuit includes: a first counter connected to a receiving module of a serial port chip and configured to record a first low level duration of a data frame received by the receiving module; a second counter configured to: receive a bit sampling pulse generated from sampling the data frame according to a current baud rate of the receiving module, and record a quantity of the bit sampling pulse in the first low level duration; a divider, connected to the first counter and the second counter and calculate a calibration baud rate according to the first low level duration and the quantity of the bit sampling pulse in the first low level duration; and a selector, connected to the receiving module and the divider and configured to output the calibration baud rate to the receiving module.

Abstract: The invention discloses a distributed atmospheric sensor-based asynchronous serial communication system. Atmospheric sensors and a host are networked through an RS-485 bus, and the host comprises a top layer module, a point-to-point communication module, a polling timing module and a polling communication module. Through a parameterized configuration mode, a host respectively sets a communicationmode, the sampling time, the number of atmospheric sensors, a communication baud rate, a communication frame protocol and a communication word protocol, configuration of different parameters of the two modes under various application requirements is realized, and asynchronous serial intelligent communication between the host and the distributed atmospheric sensors is completed under the configuration. Point-to-point communication can be achieved, communication of a polling mode can be dynamically configured according to the timing period serving as the time reference, intelligent receiving andstorage of distributed atmospheric sensor data are achieved, reliability is high, and the transmission distance is long.

Abstract: Apparatus and associated methods relate to adapting a continuous time linear equalization circuit with minimum mean square error baud-rate clock and data recovery circuit to be able to lock to the center or near center of an eye diagram. In an illustrative example, a circuit may include an inter-symbol interference (ISI) detector configured to receive data and error samples, a summing circuit coupled to the output of the ISI detector, a moving average filter configured to receive the output of the summing circuit and generate an average output, a voter configured to generate a vote in response to the average output and a predetermined threshold, and, an accumulator and code generator configured to generate a code signal in response to the generated vote. By introducing the moving average filter and the voter, a quicker way to lock to the center or near center of an eye diagram may be obtained.

Abstract: This paper describes a Universal Synchronous Asynchronous Transmitter and Receiver (USART) serial communication algorithm on the microcontroller with the MATLAB software. The appropriate configuration is necessary for serial communication and it’s obtained the time requirements of the data transmission based on the data load. The methodology of this paper applies the time measurement of the MATLAB function (“tic” and “toc”). It was sent from MATLAB to the microcontroller and returned to MATLAB. The serial transmission mode was used on this measurement by applying the Asynchronous Normal Speed and the Asynchronous Double Speed. The transmission of Double Speed Asynchronous mode having Double Baud Rate configuration than Normal Speed. The value of Baud Rate amount of 2 MBaud and the Asynchronous mode on the normal speeds are 20 data byte and 1000 data byte, it requires of transmission timing around 0,012719 seconds and 0,031394 seconds respectively. Moreover, on the normal speed asynchronous mode of 20 data byte and 1000 data byte, it requires of transmission timing around 0,0117192 seconds and 0,031719 seconds respectively. Therefore, it can get the short statement that the time requirements is proportional compared with the data load.