Abstract: In a computer network, user input is used to control the bandwidth used by particular applications. Data is sent from either a data source computer or an intermediate computer (e.g. dial-up server) to a client computer according to the user input. The allocation of bandwidth may be managed from the client computer, data source computer, or intermediate computer. The user may set a limit on the baud rate used by particular applications.

Abstract: A boot menu is provided for manual setting of serial port parameters. A serial console mode menu allows an operator to set serial port parameter values. After the user selects the serial port parameters, when the controller continues with the boot process, the serial port is initialized with the newly selected parameters. A mechanism is also provided for manual setting of serial port parameters through an administrative management window at the host. In addition, an adaptive baud rate negotiation mechanism using the Universal Asynchronous Receiver Transmitter (UART) registers in the serial port is provided. The adaptive baud rate negotiation is based on the return characters received from a break character from the serial console. The mechanism uses a look-up table for the baud rate versus the bit pattern that is received. The mechanism then sets the baud rate based on the look-up table values.

Abstract: A lighting control system having a plurality of control devices coupled to a communication link operates with a communication protocol that allows the system to expeditiously process high-priority events while operating communicate at a low enough baud rate to allow for a free-wiring topology of the communication link. The transmission of regular-priority messages is suspended if any of the control devices has a high-priority message to transmit. To signal that a control device has a high-priority message to transmit, each control device is operable to transmit a break character in a predetermined time period after the transmission of one of the digital messages. After the transmission of the break character, the transmission of the regular-priority messages on the communication link is suspended to allow the high-priority message to be transmitted quickly.

Abstract: This paper discusses the impact of flexibility when designing a Viterbi decoder for both convolutional and TCM codes. Different trade-offs have to be considered in choosing the right architecture for the processing blocks and the resulting hardware penalty is evaluated. We study the impact of symbol quantization that degrades performance and affects the wordlength of the rate-flexible trellis datapath. A radix-2-based architecture for this datapath relaxes the hardware requirements on the branch metric and survivor path blocks substantially. The cost of flexibility in terms of cell area and power consumption is explored by an investigation of synthesized designs that provide different transmission rates. Two designs are fabricated in a digital 0.13-mum CMOS process. Based on post-layout simulations, a symbol baud rate of 168 Mbaud/s is achieved in TCM mode, equivalent to a maximum throughput of 840 Mbit/s using a 64-QAM constellation.

Abstract: An analog baud rate clock and data recovery apparatus includes a first track and hold circuit that delays a received signal by one unit interval to create an odd signal; a second track and hold circuit that delays the received signal by one unit interval to create an even signal; a first comparator circuit; and a second comparator circuit. The first track and hold circuit outputs the odd signal to the first comparator circuit and the second comparator circuit. The second track and hold circuit outputs the even signal to the first comparator circuit and the second comparator circuit. The first comparator adds the odd signal to the even signal and outputs a first potential timing error. The second comparator subtracts the odd signal and the even signal and outputs a second potential timing error signal. A desired timing error signal is derived from the first and second potential timing error signals. The desired timing error signal is used to determine whether signal sampling is early or late.

Abstract: The present invention relates to ICSA Distribution Transformer Monitoring System consisting of : 32 bit ARM controller based mother board; IEC l O l, IEC-1 04, DNP3, or Modbus protocol support to communicate with master; Digital outputs with Relays (Potential free contacts) in SBO (Select before Operate) configuration; Digital inputs (optical isolated), Expandable in nature; Serial ports (RS232/RS485) to communicate with master and configuration tool; Master com' port uses RTS signal with preamble & post amble; RTS watch dog for master station communications; High accuracy on-board RTC (Real Time Clock); Master communication port baud rates configurable with jumper settings; LED indications to display Relays and Digital inputs status which LED indication may be visible from see through window on front door; The front door of DTMS having locking system; Low battery message is provided in case of battery get drained beyond 1 1V; Low battery cutoff is provided in case of battery get drained beyond 105V; 32K NV RAM for parameter and events storage Expandable in nature; Front-end software; Connectors for CT's; Onboard Temperature sensor to monitor temperature in DTMS box

Abstract: The present invention relates to methods and arrangements in a wireless communication system supporting cyclic-prefix insertion, using a symbol sequence comprising a number of samples for transmission over a radio channel that enables the handling of very large signal delay spreads. The symbol sequence is built up by a first symbol with CP and a second symbol with CP. The second symbol is a copy of the first symbol with the samples shifted in a way that makes the two adjacent symbols with CP match in regards to the sample order. The symbol sequence may also comprise a third symbol with CP or more, where the third symbol is a copy of the second symbol and with the samples shifted in analogy with the symbol shift described above. The resulting symbol sequence will thus appear as an extended continuous symbol thanks to the precise cyclic shift that matches adjacent symbols. This allows the receiver to place its FFT window anywhere during the extended symbol, e.g. at the end of the symbol sequence thus making it possible to handle a delay spread longer than the CP duration. It also allows to place e.g. two FFT windows and to combine the extracted signal into one SNR improved signal, while still handling a longer delay spread.

Abstract: A decision feedback equalizer (DFE) architecture uses feedback samples that are over-sampled with respect to the symbol rate. On-baud feedback samples are quantized with a slicer, while off-baud samples are linear, IIR samples. Both forward and feedback filters are fractionally-spaced, but adapted only at the baud instances.

Abstract: The invention discloses a steaming media data transmission method and a data transmission device thereof During the transmission process of streaming media of the method, a monitor in a buffer zone detects the bit stream baud rate of the data transmission of streaming media in real time and the size of the buffer zone is adjusted dynamically according to the bit stream baud rate detected The device comprises a protocol stack, the buffer zone and a decoder The buffer zone reads streaming media data transmitted from a server from the protocol stack and the decoder decodes the data in the buffer zone The device also comprises the monitor in the buffer zone which monitors network traffic in real time and dynamically adjusts the size of the buffer zone The steaming media data transmission method and the data transmission device thereof provided by the invention can change the size of the buffer zone according to the baud rate of actual transmission media data and reduce the waste of system resources

Abstract: Optical coherent receivers with subsequent DSP show great promise as enabling technologies for ultra-high information rate optical transmission systems. DSP alleviates the need to lock the phases of the LO and transmitter signal, which is one of the limiting factors for the use of coherent receivers in the optical domain. Various optical impairment issues can be addressed in the digital domain, in particular, nonlinearity compensation. One of the major issues still to be addressed for successful implementation of this technology is optimization of the algorithms and implementation methods used for DSP demodulation. Current DSP speeds are not high enough to process high-speed optical signals (e.g. 10 baud). Therefore, parallelization and pipelining techniques must be considered. Moreover, rigorous theoretical analysis of the performance of such receivers is being researched so the various parameters pertaining to the algorithms employed may be optimized.

Abstract: An apparatus generally having a first circuit and a second circuit. The first circuit may be configured to (i) generate an equalizer parameter in response to an input signal, the equalizer parameter causing a cancellation of post-cursor inter-symbol interference from a plurality of symbols in the input signal and (ii) generate an output signal in response to both the input signal and the equalizer parameter. The second circuit may be configured to (i) generate a target parameter signal in response to the input signal, the target parameter signal representing a mean value of a plurality of sample points of the symbols and (ii) generate a control signal in response to the target parameter signal, the control signal causing a reduction of the equalizer parameter, the reduction causing a decrease in the cancellation of the post-cursor inter-symbol interference from the symbols, wherein the apparatus does not cancel pre-cursor inter-symbol interference.

Abstract: This paper proposes an efficient coarse frequency synchronizer for digital video broadcasting - second generation (DVB-S2). The input signal requirement of acquisition range for coarse frequency estimator in the DVB-S2 is around plusmn1.5625 Mhz, which corresponds to 6.25% of the symbol rate at 25 M baud. At the process of analyzing the robust algorithm among data-aided approaches, we find that the Luise & Reggiannini (L&R) algorithm is the most promising one for coarse frequency estimation with respect to estimation performance and complexity. However, it requires many multipliers and adders to compute output values of correlators. We propose an efficient architecture identifying the serial correlator with the buffer and multiplexers. The proposed coarse frequency synchronizer can reduce the hardware complexity about 92% of the direct implementation. The proposed architecture has been implemented and verified on the Xilinx Virtex II FPGA.

Abstract: The invention discloses a method for realizing software decoding remote control of signal pulse by receiving infrared remote control signal via a serial port, which is intended to reduce the additional external intermission resource of system occupied by software decoding. The invention is mainly characterized in that: connect an OUT pin of an infrared remote control receiver to a RXD pin of the serial port; calculate the serial port baud rate according to the pulse width of the remote controller currently in use; configure tribute of the serial port, comprising the serial port baud rate; acquire the serial port data that complies the lead code of the remote controller currently in use and a user identification code; save the value of the serial port data and a corresponding serial port status register; convert the serial port data into remote control key press value according to a remote controller key press map for the corresponding relation between the value of the remote control key press, the serial port and the serial port status register. Therefore, the invention does not occupy the additional external intermission resource of system and lowers down the possibility of mistake under great load of other intermission.

Abstract: For symbol timing recovery with feedback loops, Mueller and Mueller (MM) detectors can be an attractive solution in comparison to other algorithms. This is mainly due to the fact that they are operated at baud rate, thus avoiding any performance degradation in form of the jitter floor as it is the case with zero-crossing or Gardner synchronizers as most prominent examples in this respect. However, in order to guarantee reliable results, MM trackers require the carrier phase to be established. Motivated by this background, a timing error detector for carrier-independent and non-data-aided (blind) synchronization of the symbol timing is analyzed and discussed, which needs only one sample per symbol. Assuming linearly modulated signals, the detector characteristic (S-curve) is computed exactly and verified by simulation results, with the slope in the stable equilibrium point given in closed form such that the tracking loop can be specified accordingly.

Abstract: The utility model discloses a HART protocol handhold exerciser that is based on palm computer and comprises a palm computer, a HART protocol communication port, a data memory card and connect card. The memorizing unit of the palm computer is solidified with a Chinese embedded operating system. The HART communication port receives data signals that are transmitted from the palm computer digital interface and then transforms the data signals into 1200 baud rate Bell 202 sine frequency signals that conform to the HART physical layer standard. The modulated frequency signals are superimposed into the 4 to 20mA simulated circuit through loop connector. The HART signals that return from the loop are transmitted to the modulation chip after being filtered to be transformed into digital signals that are transmitted into the palm computer. The data memory card is used in the storage of configuration procedure. The utility model has the advantages of convenient manufacturing, consumer friendly interface, simple operation and low cost. The utility model can upgrade flexibly. The digital communication conform to HART protocol standards and the utility model can meet the utilization requirements of the adjustment and maintenance of HART protocol field apparatus in the industrial process control system.

Abstract: A direct-sequence spread-spectrum communications method of de-spreading and decoding received data transmitted through an acoustic channel. A first code match filter is applied to receive data to output a first code impulse response comprising a channel impulse response modulated by a pseudo-random number bit. A second code match filter is applied to the received data to output a second code impulse response comprising the channel impulse response modulated by a message symbol bit. The first code impulse response is correlated with the second code impulse response to output the message symbol bit modulated by the pseudo-random number bit. The pseudo-random number bit is eliminated to identify the message symbol bit, thereby decoding the message symbol bit from the received data.

Abstract: This invention provides a kind of method of using the timing serial port to output the asynchronous serial port debug information on the DSP and constructs the asynchronous serial port data frame by using the structure corresponding relationship of the synchronous serial port and the asynchronous serial port data frame and the corresponding relationship of bit clock of the synchronous serial port and the baud rate of the asynchronous serial port; at the same time synchrony the frame of synchronous serial port on the DSP and logical operate the base pin which is used to deliver the data and extend the output values making it met the time sequence of the asynchronous serial port and output the asynchronous serial port debug information. Comparing with the present technology it overcomes the defect that there is no debug information output channel during the reality process for the DSP; it has the well reality and it can capture the abnormal station for the DSP and offer the trace of the location problem; the UART baud rate can be modified and it is convenience to the user.

Abstract: The utility model relates to an automatic current direction controlling device. A first input terminal is connected with a non-Schmitt trigger for receiving the input signal, while a second input terminal which is connected with a charging delay circuit in serial is connected with the first input terminal. The output terminal of the non-Schmitt trigger is connected for outputting the controlling signal. The utility model also provides an applying circuit in RS-485/422 for automatic current direction controlling and realizes the baud rate self-adaptation of the automatic current direction controlling device in the range of 300 to 115200 bps, which could automatically control the current direction of a RS-485/422 interface chip according to the output signal.

Abstract: An Ethernet transceiver comprises a physical interface used to link the television coaxial line to implement analog signal transmission, and a medium access control (MAC) layer used to be connected with MAC device to implement digital signal transmission. The invention is characterized in that the Ethernet transceiver also comprises a PMD sub-layer unit, which is positioned between the physical interface and the MAC layer interface, used to encode the high baud rate signal from the MAC layer into the low baud rate signal adapting to the reserved frequency band of the television coaxial line, and used to decode the low baud rate signal from the direction of the physical interface into the high baud rate signal. By the prior low-cost design for Ethernet chips and the existing line resources, the invention lays a good technology foundation for accomplishing the two-way reconstruction of broadcast television network access sides.

Abstract: Disclosed is a method and apparatus for composing a received symbol signal modulated with a bit reflected Gray code into bit information. According to an embodiment of the present invention, a positive integer of the received symbol signal having bits is assigned according to the Gray mapping rule, and a sign is determined. A value that is indicative of an arrangement of the bits constituting the received symbol signal is calculated. A boundary value in at least one bit group consisting of the bits constituting the received symbol signal is acquired, and a difference from an absolute value of the received symbol signal is calculated. The received symbol signal is converted into information per bit using a value of the received symbol signal based on the positive integer and the determined sign, the value that is indicative of the bit arrangement, and the difference from the absolute value. Therefore, it is possible to reduce complexity in bitwise decomposition for an iterative decoder inevitably used in a receiver.

Abstract: In this work a joint clock recovery (CR) and equalization scheme for short burst transmissions is pre- sented. The joint optimization performance may be pur- sued by means of both data aided and decision directed solutions. The novel algorithm is based on an iterative scheme, exploiting a timing error function sampled at symbol rate. The symbol timing adjustment is implemented by an interpolation filter, built according to the Farrow structure. Equalization is obtained by baud spaced zero forcing (ZF) and minimum mean square error (MMSE) linear filtering. Performance is evaluated by simulating a QPSK transceiver and simulations results are compared with the ideal solutions, for both symbol timing recovery and channel equalization, under frequency selective multipath fading channel conditions.

Abstract: The invention discloses a communication system for the call system of an elevator, comprising a main station and a substation; the main station is arranged in the main control cabinet of the elevator; the substation is divided into external calling substations arranged on each floor and an internal calling substation arranged in the elevator car; the modulation and demodulation of the communication data between the main station and the substation are realized through the low-speed power carrier communication technique with the baud rate of 200 Hz to 600 Hz. Because the communication data between the main station and the substation in the system adopt the low-speed power carrier communication technique with the baud rate of 200 Hz to 600 Hz, the communication system has the advantages of good anti-interference performance, long communication distance and low cost.

Abstract: PROBLEM TO BE SOLVED: To provide a line printer which sets a proper printing speed from the baud rate of a communication interface, and also to provide a printing controlling method. SOLUTION: The line thermal printer is equipped with a baud rate detecting means which detects the baud rate of the communication interface. When a low baud rate is detected by the baud rate detecting means (a step ST1), an upper limit value setting means sets a low printing speed as an upper limit value for the printing speed of the line thermal head (a step ST3). A driving control means also controls the printing speed of the line thermal head and the carrying speed of a recording paper so that the printing speed becomes the set upper limit value or lower, and the printing is made (a step ST5). When the baud rate is low, the printing speed of the line thermal head becomes slower, and therefore, the interruption of the printing for each printing of one line portion by the line thermal head resulting from the standing by for the receipt of printing data is avoided. COPYRIGHT: (C)2008,JPO&INPIT

Abstract: The scenery of this paper is to design a PC-based Real Time Oscilloscope, called dasiaQscilloscopepsila. Qscilloscope is capable to connect a computer with a small device via universal serial bus (USB) port for voltage signal waveform display and alteration. It detects maximum +20V to minimum -20V with the input frequency range from 0.1Hz - 1 kHz. Furthermore, it interfaces with host PC via the USB port from 9.6k to 115.2k baud rate. Qscilloscope Software Application is constructed by using Visual Basic .Net for user to interface the device with a well designed Graphic User Interface. It consists of several embedded features such as open, save and print waveform. By changing the scaling properties and graphic properties, users are allowed to modify the input signal to a desired output waveform.

Abstract: A low-complexity scheme of iterative equalisation and decoding by combining a recursive systematic convolutional code and a pulse-position modulation is proposed here. A graph- based equalisation for intersymbol interference (ISI) known at both transmitter and receiver is considered. By representing the memory channel with ISI as the factor graph and applying sum-product (SP) algorithm to this graph, a posteriori probability (APP) of the desired symbol necessary to implement iterative equalisation and decoding is derived. A partial response precoding is used to reduce the span of ISI from a possible infinite number of two baud periods. This precoding scheme makes the factor graph of memory channel cycle-free, and SP algorithm for combating ISI converges to an optimum detection. Numerical results show that the proposed low-complexity strategy has almost the same performance as the optimum turbo equalisation.

Abstract: Extraction of correct timing error information is very important for high-speed digital transmission systems. In this letter, a novel effective-data-sequence-based timing error detector (EDS-TED) is presented for a baseband transmission system using nonlinear Tomlinson-Harashima precoding (THP), such as 10GBASE-T. The key idea of our TED is to minimize the mean square error between the received and desired EDS, rather than between the transmitted data signals. This formulation can exploit the autocorrelation between the EDS signals and extract the timing information embedded in the received signal. Moreover, the proposed architecture can lead to a simple and feasible circuit implementation. Simulation results show that a timing loop based on the proposed EDS-TED achieves a superior performance over traditional TED in terms of the peak-to-peak jitter and the TED gain.

Abstract: A method and system of sample recovery is disclosed. In one embodiment, a method includes selecting initially in an arbitrary manner, a current symbol from a sequence of input samples, comparing a symbol timing estimate associated with the current symbol to a predetermined threshold, selecting a future symbol strobe that is ahead at an interval equivalent to a predetermined interval based on the comparison of the symbol timing estimate to the predetermined threshold, selecting a future symbol from the sequence of samples corresponding to the future symbol strobe, assigning the future symbol to the current symbol, which is the recovered symbol, rearranging the recovered symbols to form Pulse Code Modulated (PCM) samples of a bandlimited signal at a sample rate which is derived from the recovered symbol rate, and resampling at the sample rate of the receptor block which receives the recovered PCM samples.