Abstract: A home networking transmitter (100), receiver (200), station (300), network manager (404), network (400) and method adapted to network devices (344/336/338/346) over phone lines (406) in a home. A bandwidth other than the 4 to 10 MHz band defined in the HomePNA 2.0× specification and a Baud rate higher than 4M baud may be used for communications between a plurality of devices (334/336/338/346). PHY and MAC layers are improved to increase the performance of home phone line networks. Advantages in the PHY layer include numerous higher symbol rates, higher constellations, variable power level, error correcting codes, byte interleaving, ISI-free pulse shape and pre-equalization. Advantages in the MAC layer include managed bandwidth resources allocation, guaranteed quality of service for latency sensitive applications, solicited grants, support to devices with low power consumption and support to device with low processing power.

Abstract: A system comprising a first device and a second device having an electronic data card associated therewith, information on the electronic data card being useable by and accessible by the first device, wherein the first device is arranged to control the operating characteristics of the electronic data card of the second device. Thus the first device may power up/down the electronic data card, reset the electronic data card or change the clock or baud rate associated with the electronic data card.

Abstract: An IF strip for a wireless receiver supports a variable baud rate by changing analog filter bandwidth. Sliding and step adaptive dynamic range are both used at IF to dissipate only the necessary power at prevailing channel conditions. A combination of VGA and PGA is developed for 64-QAM. The total signal processor draws an average of 16 mA from 3.3 V and a peak of 73 mA. The differential input noise is as low as 3.9 nV//spl radic/Hz, while maximum IIP3 is +22 dBm with respect to 100 ohms.

Abstract: An apparatus ( 30 ) for and method of synchronizing OFDM signals utilizes a single baud to provide synchronization in time, frequency, and per-subcarrier rotation ( 201 ). Timing and fractional subcarrier frequency synchronization may be obtained from either a known or unknown (e.g., data symbol) baud having known symmetry properties. Because all three synchronization tasks may be accomplished utilizing a single sync baud, the present invention spectrally efficient. A differential correlation metric is utilized to efficiently provide integer subcarrier frequency synchronization and per-subcarrier rotation synchronization.

Abstract: A method and signal therfor embodied in a carrier wave for sending information from transmit stations to receive stations over a transmission medium of a frame-based communications network. The information is sent in transmit frames having a frame format comprising a fixed rate header, followed by a variable rate payload, followed by a fixed rate trailer. The fixed rate header includes a preamble. The preamble has a repetition of four symbol sequences for facilitating power estimation, gain control, baud frequency offset estimation, equalizer training, carrier sensing and collision detection. The preamble also includes a frame control field. The frame control field has scrambler control information for frame scrambling initialization, a priority field to determine the absolute priority a transmit frame will have when determining access to the transmission medium, a payload encoding field which determines constellation encoding of payload bits in the variable rate payload, and a header check sequence for providing a cyclic redundancy check. The variable rate payload is transmitted pursuant to dynamic adjustable frame encoding parameters for improving transmission performance for a transmit frame being transmitted from a transmitting station to a receiving station. The header also includes a destination address field, a source address field and an ethertype field.

Abstract: A code symbol reading device includes a portable housing that contains a light source. Light from the light source is projected into a scan field external to the housing and onto a code symbol on an object located within the scan field. The light reflected off the code symbol is detected within the housing to produce scan data that is indicative of the detected light intensity. The scan data is processed to detect and decode the code symbol and to produce symbol character data that are representative of the decoded code symbol. A data packet utilizing the symbol character data is synthesized and modulated onto a carrier signal that is transmitted to a base unit where the carrier signal is demodulated and the data packet recovered. The received data packet is analyzed to recover the symbol character data, and an acknowledgment signal is produced to acknowledge the receipt of the symbol character data at the base unit.

Abstract: An autobaud mechanism is executed by transceivers coupled to opposite ends of a communication loop, such as an extended range SDSL loop, to resolve the maximum data rate that can be supported by the loop, using signal power and quality measurements to first estimate the length of the SDSL loop and thereafter iteratively adjust baud rate and/or number of bits/per baud, as necessary, to realize an SDSL baud rate that will ensure error-free transmission over the loop.

Abstract: A satellite-based communications system (1) and a method for operating a satellite-based communications system is disclosed. The communications between a user terminal (10) and a gateway (20) occur using an uplink band of frequencies between the user terminal to at least one satellite (3) and in a downlink band of frequencies between the at least one satellite and the user terminal. The system includes first transceivers (10) in the user terminal for transmitting and receiving voice and data in the first and second bands of frequencies using, for example, a conventional MSS maximum data rate of 9600 Baud); and second transceivers for transmitting and receiving data in the first and second bands of frequencies using a second data rate that exceeds the maximum data rate. The gateway is a dual gateway (20) that includes a first interface to voice and data signals and circuitry for transmitting and receiving the voice and data signals using the maximum data rate, and further includes a second interface to data signals and circuitry for transmitting and receiving the data signals using the data rate that exceeds the maximum data rate. User terminal registration and control signals are transmitted and received using the first transceiver. The first transceiver is a portion of a Mobile Satellite Service (MSS) terminal that is detachable from the user terminal (10) for being operated as a stand-alone unit for transmitting and receiving voice and data signals in the first and second bands of frequencies using the maximum data rate.

Abstract: A system and a method for simple and robust baud-rate timing recovery suitable for jointly operating with a decision-feedback equalizer are disclosed. Timing functions for timing recovery are extracted only from filter coefficients of feed-forward and feedback filters. The relation between the coefficients of feed-forward filter and the impulse response is derived under a zero-forcing condition while the relation between the coefficients of the feedback filter and the impulse response is known. Based on the relations, several timing functions with varied degrees of computation are derived, which can drive the sampling instances approximately at the peak point of the channel impulse response. Since the derived timing functions uses equalizer coefficients, they work jointly with equalization even without using a training sequence. Simulation results over 5-m and 100-m UTP Category-5 cables at 125M Baud show fast and robust timing recovery operation in a phase-locked loop.

Abstract: An analog input to an interpolation scheme for a digital signal processing receiver is digitized by an oversampling sigma-delta modulator running at a clock frequency that is a multiple of the nominal baud rate. The digitized signal sample stream and a delayed version thereof are shifted through finite impulse response (FIR) filters. The outputs of the FIR filters are coupled to a linear interpolator at a time determined by a carry-out of a divide-by-M counter, so as to decimate the digitized inputs to the FIR filters by the ratio of the oversampling clock to the baud clock. The control path to the interpolator includes a digital phase locked loop containing a linear canceler, to which data from an echo canceler and data decisions from an equalizer are supplied, and from which a timing error input is supplied to a loop filter. The output of the loop filter is supplied to a threshold comparator which outputs an add/delete count signal to a modulo N up/down counter that controls the coupling of samples to the interpolator. At baud time, the two decimated FIR filter samples A and B are subjected to a linear interpolation operator A+(B−A)*n/N, where n is a count value provided by the up/down counter of the total number of times that the comparator has initiated an add or delete command, and serves as a software pointer to the signal value to be interpolated.

Abstract: A statistical simulation method is introduced to estimate the sector error rate (SER) of proposed triply concatenated coding systems for magnetic hard disk drives. The outer code is a standard interleaved Reed-Solomon code. The 'middle' codes are run length limiting codes used to demonstrate the effect of error propagation. The inner code(s) are block codes with 1 or 3 parity check bits. First, a baud rate simulation is used to estimate sufficient statistics to extrapolate ECC performance. Second, a Monte Carlo error event simulator generates error instances which are simply checked for correctability. In all code combinations the apparent SNR gains when considering error (or bit) event rates are considerably lessened or completely lost when considering SER.

Abstract: A transceiver method and signal therefor embodied in a carrier wave for sending information from transmit stations to receive stations over a transmission medium of a frame-based communications network. The information is sent in transmit frames having a frame format comprising a fixed rate header, followed by a variable rate payload, followed by a fixed rate trailer. The fixed rate header includes a preamble. The preamble has a repetition of four symbol sequences for facilitating power estimation, gain control, baud frequency offset estimation, equalizer training, carrier sensing and collision detection. The preamble also includes a frame control field. The frame control field has scrambler control information for frame scrambling initialization, a priority field to determine the absolute priority a transmit frame will have when determining access to the transmission medium, a payload encoding field which determines constellation encoding of payload bits in the variable rate payload, and a header check sequence for providing a cyclic redundancy check. The variable rate payload is transmitted pursuant to dynamic adjustable frame encoding parameters for improving transmission performance for a transmit frame being transmitted from a transmitting station to a receiving station. The header also includes a destination address field, a source address field and an ethertype field.

Abstract: A jitter measurement method using a down-mixing or down-converting topology in a jitter measurement system preserves the jitter UI rather than the jitter seconds. An input serial data stream at a high baud, after conversion from NRZ to RZ if necessary, is mixed with a stable local oscillator frequency that is close to that of the high baud. The difference between the high baud and the local oscillator frequency is passed by a filter to a clock recovery circuit, to an amplitude modulation removal stage or to a digitizer as a lower rate serial stream. The clock recovery circuit recovers a lower rate clock from the lower rate serial stream upon which the jitter measurement is performed by a jitter measurement stage. The amplitude modulation removal stage converts the lower rate serial stream to a lower rate NRZ signal upon which the jitter measurement is performed directly by the jitter measurement stage or via the clock recover circuit. The digitizer output is processed by a digital signal processor, implementable as a field programmable gate array, to perform algorithms corresponding to the hardware implementation as well as compensating for non-linearities in the down conversion process. The local oscillator and/or IF lowpass filter may be tunable to provide an adjustable baud jitter measurement system at high bauds.

Abstract: In a communications system such as a wireless code division multiple access (CDMA) communications system, an interference-compensated information symbol (rn2(t)) is generated from a source information symbol based on knowledge of an information symbol (d11(t)) and a first code (Q11(t)) used to generate a first coded signal. The first coded signal and a second coded signal representing the interference-compensated information symbol encoded according to a second code are then concurrently transmitted. In one embodiment, a composite signal is generated from at least one information symbol according to at least one code from a first group of codes of a set of quasi-orthogonal codes. An interference-compensated information symbol is then generated from a source information symbol, the composite signal and a code from a second group of codes of the set of quasi-orthogonal codes. The second coded signal represents the interference-compensated information symbol encoded according to the code from the second group, and is transmitted concurrently with transmission of the first coded signal. Preferably, the interference-compensated information symbol is generated by integrating (523) a product (521) of the composite signal and the complex conjugate of the code from the second group over a symbol interval (T), scaling the integrated product by a scaling factor, and subtracting (524) the scaled integrated product from the source information symbol to generate the interference-compensated information symbol (rn2(t)).

Abstract: This paper presents a new technique which allows high baud rate with low operation speed of the synchronizer. This technique is based on parallel processing. What is done by only one clock operating at the baud rate can be done by two clocks operating only at half rate. By generalizing we propose versions of clock recovery circuits operating at the ratio 1/2/sup n/ of the data rate. Thus we obtain circuits transmitting at very high data rate but operating at very low frequency. The proposed circuits which are transition sensitive (digital) are compared with the traditional level sensitive (analog).

Abstract: A sampling system and method of the read channel of optical storage system are disclosed, which comprises at least an analog-to-digital sampling device, a time recovery interpolation module, a 2T time equalization module, a DC bias control circuit, a two-times factor interpolation circuit module and a serial detector The analog-to-digital converter device is to read the analog signal of the storage media with the frequency half or a little more than half of the channel baud rate, the time recovery interpolation module proceeds the interpolation to the sample outputted from the analog-to-digital sampling device, and proceed the high-frequency signal compensation with the 2T time equalization module, replenish the middle data between the adjacent data by the two-times factor interpolation circuit module with interpolation, then output the bit data of zero error rate by serial detector, wherein the DC component signal can be removed at any time before said two-times factor interpolation circuit module and after the analog-to-digital sampling

Abstract: PROBLEM TO BE SOLVED: To obtain a system capable of suppressing the occurrence probability of erroneous detection with a simple system constitution by setting the period of a transfer clock signal for transmission and the period of a data sampling signal for reception to baud rate set values. SOLUTION: A baud rate set value equal to n times the clock period of internal operations is set in a rewritable manner to set the period of a transfer clock signal for transmission and the period of a data sampling signal for reception to this baud rate set value. In a transmitting operation, e.g. when the count value of a counter 1 matches a set value (n) held by a register 3, a comparator 2 outputs a coincidence pulse, which resets the counter 1 through an OR circuit 12. As the result, the transfer clock signal of 1/n frequency of an operation clock signal is formed and a parallel/serial converter 7 sample-holds serial output data outputted from a microcomputer 300 at the rising edge of this transfer clock signal for outputting.

Abstract: The method involves remotely resetting a memory circuit of an electric operating device with a serial interface, whereby the baud rate of the reading/operating instrument for transmitting of a reset instruction is lowered with respect to the remaining data transmission signals, so far, that the bit length of the reset instruction exceeds the length of a data group of the remaining data transmission signals, limited through a stop signal. At least one bit of the reset instruction is transmitted, which is recognised by a detection circuit in the electric operating device due to its bit length, as an instruction triggering a reset signal.

Abstract: The clock signal recovery method uses Baud rate sampling of an input signal (u) via a sampler (SR) coupled via an A/D converter (ADC), a feed forward equalizer (FFE) and a summator (SUM) to a decision stage (DEC), providing a decision signal fed via an adaptive decision feedback equalizer (DFE) to the summator and to one input of 2 phase detectors (PD1,PD2), receiving the outputs of the A/D converter and the summator at their second inputs respectively. The phase detectors are selectively coupled via a loop filter (LF) to a digitally-controlled oscillator (DCO) connected to the clock input of the sampler. An Independent claim for a clock signal regeneration circuit for a receiver is also included.

Abstract: A symbol is coded by being converted into a first code. The code is then mapped to a second code in dependence on the nature of the information represented by the symbol. In this way, the efficiency of the coding is increased. The coded symbol is decoded by means of a reciprocal mapping process.

Abstract: PURPOSE: An apparatus and a method for controlling a LCD of a mobile terminal in a D-TRS(Digital Trunked Radio Signal) are provided to easily construct circuit and control the LCD by controlling the LCD with serial communication. CONSTITUTION: A transmit data buffer(101) temporarily stores a transmit data transmitted through a data bus and sets a TXIF(Transmit Interrupt Flag). The first AND gate(102) performs AND with the TXIF and a TXIE(Transmit Interrupt Enable), and outputs the result as an interrupt signal. A baud rate clock generator(103) generates baud rate clock for determining baud rate. The second AND gate(104) performs AND with the baud rate clock and a TXEN(Transmit Enable), and outputs the result as a register control signal. The third AND gate(105) performs AND with TX8/TX9 for determining 8 bit transmission or 9 bit transmission and TXD8 for additional 1 bit when transmitting 9 bit transmission. A serial shift register(106) determines a transmission rate with the clock output from the second AND gate(104) and outputs 8 bit data of the transmit data buffer(101) and 1 bit data of the third AND gate(105) as serial data. A buffer control part(107) outputs the output data of the serial shift data register(106) with a LCD and controls the transmit data buffer(101) according to the data state of the serial shift register.

Abstract: The invention describes methods and systems designed to reduce or avoid the effects of longitudinal capacitive imbalance in transmission systems that transmit signals using differential transmission, such as transmission systems comprised of a twisted wire pair transmission path (130). The methods and systems of the present invention optimize the transmission bandwidth that is utilized, including for example, by selecting an increased modulation density format or baud rate (201) in preference to selecting a higher portion of frequency spectrum (202).