TL;DR: In this article, an adaptive coding scheme for the coded digital transmission of images was proposed, which includes an adaptive transmitter (101) having an image coder (109) which is operable at multiple image coding rates, a channel coder(111), and a channel status monitor (115) which responds to changes in the quality of the communications channel by varying one or more of the image coding rate, the channel coding rate and the power, the baud rate, and the image delivery rate.
Abstract: An adaptive arrangement and method for the coded digital transmission of images includes an adaptive transmitter (101) having an image coder (109) which is operable at multiple image coding rates, a channel coder (111) which is operable at a plurality of channel coding rates, and is further operable to provide a plurality of power outputs, baud rates, and a plurality of image delivery rates. The transmitter (101) further includes a channel status monitor (115) which monitors the communication channel (105) connecting the transmitter (101) to a receiver (103). The channel status monitor (115) responds to changes in the quality of the communications channel by varying one or more of the image coding rate, the channel coding rate, the power, the baud rate, and the image delivery rate.
TL;DR: In this article, a method of coding parallel data for transmission while maintaining a predetermined baud rate is proposed, where the predetermined rate is maintained by providing an adequate number transmission links rather than increasing baud rates.
Abstract: A method of coding parallel data for transmission while maintaining baud rate includes the steps of providing a plurality of uncoded data blocks having a predetermined baud rate, demultiplexing the data blocks to sequentially distribute the data blocks to encoders, encoding the data blocks at the predetermined baud rate, and serializing the coded data blocks for serially transmitting data at the predetermined baud rate. A system for coding parallel data for serial transmission while maintaining baud rate is included wherein the predetermined baud rate is maintained by providing an adequate number transmission links rather than increasing baud rate.
TL;DR: In this paper, a rate adaptive digital subscriber line (XDSL) communication system and method are disclosed, where an XDSL link is trained at a data rate set by a baud rate and a constellation size, and if the trained data rate will not provide the desired bit error rate, a new data rate is selected using the empirical data and the actual operating characteristics.
Abstract: A rate adaptive digital subscriber line (XDSL) communication system and method are disclosed. An XDSL link for XDSL equipment is trained at a data rate set by a baud rate and a constellation size. Actual operating characteristics of the XDSL equipment are then obtained from parameters for the trained XDSL link. One or more rate adaptive data tables storing empirical data for performance of the XDSL equipment are accessed. Then, it is determined whether the trained data rate will provide a desired bit error rate using the actual operating characteristics and the empirical data from the accessed one or more of the rate adaptive data tables. In one embodiment, if the trained data rate will not provide the desired bit error rate, a new data rate is selected using the empirical data and the actual operating characteristics. Then, the XDSL link is trained using the new data rate, and the process is repeated. Further, in one embodiment, the actual operating characteristics used comprise the actual receiver gain and signal-to-noise ratio, and the empirical data comprises specified receiver gains, signal-to-noise ratios, baud rates and constellation sizes used to achieve a desired bit error rate.
TL;DR: In this article, a personal information device is provided in the form of a PCMCIA card and includes an adaptable docking station that can communicate with a computer by using a controller and changing the baud rate of data serially supplied to the computer.
Abstract: A personal information device is provided in the form of a PCMCIA card and includes a PCMCIA I/O port that is adapted to be coupled to a PCMCIA port of a computer, a first memory that is directly accessible by the computer via the PCMCIA I/O port, second and third memories that are not directly accessible to the computer, and a controller. When the personal information device is inserted into the computer's PCMCIA port, the first memory directly receives and stores therein reprogramming data supplied by the computer. Immediately after the data is downloaded, or alternatively, upon disconnection of the personal information device from the computer, the personal information device's controller transfers to the second memory reprogramming code included in the reprogramming data stored in the first memory, executes the reprogramming code stored in the second memory, and then programs the third memory by utilizing the application code included in the reprogramming data stored in the first memory in accordance with the reprogramming code being executed. The downloaded application code may include organizer application code for the end user, diagnostic code or other types of code. In addition to being able to interface with a computer via the computer's PCMCIA port, the personal information device may communicate with a computer by using a docking station that includes therein a controller and that is capable of changing the baud rate of data serially supplied thereto so as to allow a computer and a personal information device communicating at different baud rates to serially communicate with one another.
TL;DR: In this article, a QAM data signal timing recovery loop feedback element provides a fixed sampling time offset adjustment to two continuously variable digital rate interpolators/decimators to produce a quadrature output stream at a programmed rational rate multiple of the actual baud rate of the received data signal.
Abstract: A QAM data signal timing recovery loop feedback element provides a fixed sampling time offset adjustment to two continuously variable digital rate interpolators/decimators to produce a quadrature output stream at a programmed rational rate multiple of the actual baud rate of the received data signal. The continuously variable digital rate interpolators/decimators are configured at startup so as to produce output streams at the same programmed rational rate multiple of the nominal baud rate of the anticipated received data signal, assuming the fs sample timing offset adjustment stream provided by the timing recovery feedback element to be identically 0. The “nominal” fixed sampling rate fs of the received analog input signal need not be rationally related to the nominal baud rate of the anticipated received data signal.
TL;DR: In this paper, a frequency-diverse single-carrier modulation scheme was proposed to extend the usable SNR range of severely distorted channels, where the symbol baud rate is selected in order that unusable portions of the frequency response of the transmission channel are mapped onto usable portions of a corresponding channel.
Abstract: The present invention provides a frequency-diverse single-carrier modulation scheme that extends the usable SNR range of severely distorted channels. This scheme is advantageous for applications in which when the SNR is low and the transmitted spectrum contains unusable regions (e.g., spectral nulls due to radio-frequency interference ingress or egress). In one embodiment, the symbol baud rate is selected in order that unusable portions of the frequency response of the transmission channel are mapped onto usable portions of the frequency response of the transmission channel.
TL;DR: In this paper, a sub-baud rate write circuit was proposed for sub-sampled read/write channels, where the object is to reduce the cost and complexity by clocking the entire channel at a frequency significantly below the baud rate.
Abstract: A sub-baud rate write circuit is disclosed which writes RLL encoded channel data to a disk storage medium using a write clock frequency significantly below the baud rate. This allows for a higher channel data rate without increasing the cost and complexity of the write circuitry. The write circuitry operates by re-encoding the RLL encoded channel data according to a particular mapping to generate write data at the write clock rate, and then writing the write data to the disk at appropriate phase delays. The phase delays are generated by passing the write clock through an array of delay circuits. The resulting write signal is the same as if the RLL encoded data were written to the disk using a baud rate write clock. The write circuitry of the present invention is ideally suited for use in a sub-sampled read/write channel where the object is to reduce the cost and complexity by clocking the entire channel at a frequency significantly below the baud rate.
TL;DR: In this article, an improvement to a Reed Solomon (RS) coding scheme was proposed, where the RS encoder (32) and decoder (71) are initiated based upon counting a number of timing, baud, or byte cycles from a known time stamp.
Abstract: An improvement to a Reed Solomon (RS) coding scheme wherein the RS encoder (32) and decoder (71) are initiated based upon counting a number of timing, baud, or byte cycles from a known time stamp. The time stamp can be for example, a Tomlinson coefficient exchange frame whereby at the end of a Tomlinson coefficient exchange frame, a counter (35) in both transmitter and receiver is actuated to begin counting a number of baud cycles. Alternatively, the counter may be initiated upon the receipt of a particular byte. Once the appropriate number of baud cycles or bytes have elapsed, the RS encoder (32) and decoder (71) will begin operation, thus ensuring that both RS encoding and decoding occur at the proper time, without the use of any additional framing bits.
TL;DR: In this paper, the authors propose a method of efficiently demodulating and isolating a signal within a fixed possibly wider band spectral region, having any of a wide range of baud rates.
Abstract: A method of efficiently demodulating and isolating a signal within a fixed possibly wider band spectral region, having any of a wide range of baud rates. The signal is sampled at a fixed, first frequency which remains fixed no matter what the baud rate. Thus, the sample rate does not necessarily correspond to the desired baud rate. The sampled signal is then demodulated and low pass filtered to create baseband samples at the first frequency, which are then subject to user-specified arbitrary rate change in a continuously variable interpolator/decimator (continuously variable digital delay (CVDD) device), and decimated by a programmable power of 2, to produce samples at a second frequency. The second frequency is preferably determined to be a whole number multiple of the desired baud rate, e.g., twice the desired baud rate. The samples are equalized to produce output symbols at the target baud rate. Based on this method, a demodulator can receive signals of varying bandwidth and baud rates at arbitrary spectral locations within a possibly wider bandwidth aggregate channel span, and can adapt its target baud rate for each signal to be the actual baud rate of the derived incoming data signal within the possibly wider bandwidth aggregate channel span.
TL;DR: An autobaud method for automatic detection of baud rate and character configuration of a received asynchronous serial data stream by detecting a first predetermined two character sequence in uppercase and lowercase form, notably "AT" and "At", from patterns of signal states and their durations, also provides for detecting a second predetermined two sequence of "A/" and "a/" and for substantially immediate automatic echoing of the first and second predetermined character sequences if autoechoing is enabled as discussed by the authors.
Abstract: An autobaud method for automatic detection of baud rate and character configuration of a received asynchronous serial data stream by detecting a first predetermined two character sequence in uppercase and lowercase form, notably "AT" and "at", from patterns of signal states and their durations, also provides for detecting a second predetermined two character sequence of "A/" and "a/" and for substantially immediate automatic echoing of the first and second predetermined character sequences if autoechoing is enabled. The baud rate and character configuration used for subsequent characters is not be changed unless, after the autobaud function is enabled, the first predetermined two character sequence in either uppercase or lowercase form is received, and a different baud rate and/or character configuration is determined from the received pattern of signal states and their durations. The baud rate is determined by measuring the duration of a signal state begun by an apparent transition from a stop bit or idle state, and determining whether the measured duration falls within any of a set of predetermined bit time ranges or legal windows, each corresponding to a different baud rate of a set of predetermined standard baud rates.
TL;DR: In this article, a two-wire RS-485 signal repeater was proposed to increase the signal strength of the RS-232 signal in the two-way RS-486 network.
Abstract: A method and a device for half duplex serial signal control with multiple baud rates and multiple configurations comprises RS-232 interface circuit, RS-485 interface circuit, power circuit, protective circuit, and logical control circuit. A brand new controlling method is applied to the receiving/transmission signal control wire on the RS-485 interface circuit so that the programmable logic controllers (PLCs) in the two-wire RS-485 network can be set at different baud rates and different configurations for RS-232 communication. That is, programmable logic controllers (PLCs) from different manufacturers, using different communication speed can connect one another as well as a personal computer. A signal converter transforms the RS-232 interface signal to the RS-485 interface signal for each PLC, passes through the RS-485 signal in the two-wire RS-485 network, and finally transforms the RS-485 signal to RS-232 signal for the connected computer. A PC can therefore connect to PLCs from different manufacturers, using different communication speed. When the distance between each PLC is far apart, the two-wire RS-485 signal repeater in the present invention can extend the network and increase signal strength so that long distance communication is allowed.
TL;DR: In this article, a method for automatically determining the baud rate of a serial data transmission comprises the steps of setting a receiving device to a first-baud rate, processing a first data word received by the receiving device, and possibly further information to determine the second-bit rate of the data transmission.
Abstract: A method for automatically determining the baud rate of a serial data transmission comprises the steps of setting a receiving device to a first baud rate, processing (65) a first data word received by said receiving device and possibly further information to determine said baud rate of said data transmission, possibly setting (68) said receiving device to a second baud rate in order to enable said receiving device to find the beginning of a subsequent data word in said serial data transmission, and possibly setting (74) said receiving device to said determined baud rate. A corresponding apparatus and a mobile telephone each employs this method. The invention provides an autobauding function which causes little expense in terms of hardware and processing time, and which will correctly synchronize with the serial data transmission even if the transmitted data words immediately follow each other.
TL;DR: In this paper, an asynchronous serial port with a serial clock derived from the processor clock is used to improve the reception of the asynchronous data, because the frame length more nearly matches the ideal baud rate frame length.
Abstract: A microcontroller provides an asynchronous serial port with a serial clock derived from the processor clock. Although the serial clock cannot be exactly programmed to yield an ideal frame length at a particular baud rate, an additional register is provided for tuning the frame length. Each transmitted asynchronous serial frame is stretched by a number of either serial clock phases or processor clocks defined in the tuning register. This provides for improved reception of the asynchronous data, because the frame length more nearly matches the ideal baud rate frame length.
TL;DR: In this paper, a method of automatically detecting the baud rate of an input signal and an apparatus using the method of automatic detection of a first and second transition of the input signal is presented.
Abstract: A method of automatically detecting the baud rate of an input signal and an apparatus using the method. A counter is started upon detecting a first transition of the input signal. The counter is stopped upon detecting a second transition of the input signal. After the counter is stopped, the measured count in the counter represents the duration between the first and second transitions of the input signal. The measured count is compared to a plurality of expected counts to determine which of the plurality of expected counts has a value closest to the measured count. The input signal is sampled using a baud rate based on the expected count having a value closest to the measured count.
TL;DR: In this article, an all digital timing recovery circuit for optical disk storage systems is described. But the circuit is based on a single-input single-output (SISO) system, and the data detector, such as a Viterbi sequence detector, processes the synchronous sample values to generate an estimated binary sequence representing the recorded binary sequence.
Abstract: A sampled amplitude read channel for optical disk storage systems is disclosed comprising an all digital timing recovery circuit. The RF read signal from the read head is sampled asynchronous to the baud rate and the asynchronous sample values are interpolated to generate sample values that are substantially synchronous to the baud rate. A data detector, such as a Viterbi sequence detector, processes the synchronous sample values to generate an estimated binary sequence representing the recorded binary sequence. The timing recovery circuit comprises a baud rate estimator for estimating the baud rate relative to the sampling rate, wherein the estimated baud rate is used to initialize a timing recovery loop filter at the end of seek operations. The all digital timing recovery circuit and baud rate estimator enable the storage device to begin reading the user data immediately after a seek operation, rather than wait for the CLV servo loop to acquire the target spindle speed.
TL;DR: In this article, a system and method for demodulating digital information from a modulated signal that can be represented in a signal space diagram as an odd constellation of sample points is presented.
Abstract: A system and method for demodulating digital information from a modulated signal that can be represented in a signal space diagram as an odd constellation of sample points. The system comprises filtering means for receiving the modulated signal that includes means for rotating the received sample points 45° clockwise on the signal space diagram such that decision or neighborhood regions can be drawn having borders that are either parallel or perpendicular to the axes of the signal space diagram. As a result, a slicer can easily extract the symbol information from the rotated sample points with a minimum of computational complexity. Moreover, and perhaps most importantly, the rotation is accomplished through a one time modification of the tap coefficients used by the filtering means thus eliminating any additional processor real time required to perform the rotation. Indeed, through this modification of the filtering means, the present invention can be used to effectively and efficiently demodulate odd constellations without any dependence on the baud rate.
TL;DR: In this paper, a time division multiple access digital communications system (12) is provided, where a base station (14) is configured to generate a receive baud clock ( 86 ) and has a receiver ( 18 ) and a transmitter (20 ).
Abstract: A time division multiple access digital communications system ( 12 ) is provided. The system ( 12 ) has a base station ( 14 ) configured to generate a receive baud clock ( 86 ) and has a receiver ( 18 ) and a transmitter ( 20 ). The system also has a subscriber unit ( 16 ) configured to generate a transmit baud clock ( 50 ), and has a transmitter ( 28 ) and a receiver ( 26 ). The subscriber unit transmitter ( 28 ) is configured to transmit a reverse channel signal ( 54 ) that incorporates the transmit baud clock ( 50 ) as a component thereof. The base station receiver ( 18 ) is configured to receive the reverse channel signal ( 54 ) from the subscriber unit ( 16 ) and produce a phase-error signal (μ′) in response to a phase difference between the transmit baud clock ( 50 ) and the receive baud clock ( 86 ). The base station transmitter ( 20 ) is configured to transmit the phase-error signal (μ′) to the subscriber unit receiver ( 26 ). The subscriber unit transmitter ( 28 ) contains an interpolator ( 122 ) configured to adjust the phase of the transmit baud clock ( 50 ) in response to the phase-error signal.
TL;DR: In this paper, a method of decrypting data comprising encrypting bit-wise data, using a first plural bit mask, modulating the data into symbol format, and transmitting the symbol format data to a receiving apparatus, was proposed.
Abstract: A method of decrypting data comprising encrypting bit-wise data, using a first plural bit mask, modulating the data into symbol format, and transmitting the symbol format data to a receiving apparatus, in a receiving apparatus, rotating a current received symbol sample by an amount equal to one of (i) its difference in phase from an immediately preceding received symbol sample toward the phase of the immediately preceding received symbol sample phase, and (ii) by an amount equal to estimated carrier phase towards zero phase, generating a second bit mask subset derived from values of the first bit mask, comprising plural bits for each symbol, reflecting the rotated symbol by a phase defined by the plural bits to form a symbol which is devoid of encryption, and providing the symbol devoid of encryption to a soft-decision decoder.
TL;DR: In this paper, the optimal baud rates for Rate Adaptive Digital Subscriber Line (RADSL) are provided for loops with an 1 kft length difference, and a set of baud rate with 200 KHz spacing.
Abstract: Baud rates for Rate Adaptive Digital Subscriber Line (RADSL) are provided. Optimal baud rates are about 200 KHz apart for loops with an 1 kft length difference. By adapting a set of baud rates with 200 KHz spacing a performance within 0.5 dB of the optimal performance may be maintained.
TL;DR: In this paper, a universal asynchronous receiver and transmitter includes a transmit clock supplier and a receive clock generator, and the clock supplier provides an opposite system with a baud clock in response to its baud rate before transmitting data to the opposite system.
Abstract: A universal asynchronous receiver and transmitter includes a transmit clock supplier and a receive clock generator. The clock supplier provides an opposite system with a baud clock in response to its baud rate before transmitting data to the opposite system. The receive clock generator generates a baud clock in response to a baud rate supplied from the opposite system and receives data.
TL;DR: A bit synchronisation algorithm for channels with data dependent noise which operates with one sample per symbol is presented and it is shown that significant improvements over the M&M algorithm can be obtained in practical optical channels.
Abstract: A bit synchronisation algorithm for channels with data dependent noise which operates with one sample per symbol is presented. The algorithm uses the same information as the Mueller and Muller (M&M) algorithm, and is optimised for operation with data dependent noise. The performance is derived and it is shown that significant improvements over the M&M algorithm can be obtained in practical optical channels.
TL;DR: In this paper, a digital variable rate demodulator within a receiver operates close to the Nyquist rate, and the samples of an incoming data signal are divided into phases and combined into phase vectors. Intermediate points within a given phase vector are determined by interpolation.
Abstract: A digital variable rate demodulator within a receiver operates close to the Nyquist rate. This serves to recover correct timing and filter adjacent channels. The samples of an incoming data signal are divided into phases and combined into phase vectors. Intermediate points within a given phase vector are determined by interpolation. The data is then converted into a weighted sum for the purpose of decimating down to the baud rate. The signal-to-noise ratio is then optimized by estimating the likelihood of occurrence of a given symbol within the waveform and filtering the near Nyquist data rate down to a one sample per symbol data rate.
TL;DR: In this paper, a data decoding scheme was proposed to recover the data state of data represented by the code symbol within the encoded data stream by selecting the minimum of the generated error vectors.
Abstract: A data decoding scheme operates on individual code symbols within an encoded data stream, enabling data to be recovered from the code symbols at a high rate. The decoding scheme, typically included within a receiver of a digital communication system or data network, does not rely on processing and storing multiple code symbols and is unencumbered by storage memory elements and decoding rate limitations associated with receiving and processing blocks of multiple code symbols. The decoding scheme generates bit sequences corresponding to each alternate data state of a received code symbol. Error vectors are generated as a result of comparing each of the generated bit sequences to the received code symbol. The data state of data represented by the code symbol within the encoded data stream is recovered from the code symbol by selecting the minimum of the generated error vectors.
TL;DR: In this article, a start-stop synchronization data transmission method was proposed to realize a stable startstop synchronization communication even with a clock outputted from an oscillator whose oscillation frequency accuracy is low.
Abstract: PROBLEM TO BE SOLVED: To provide a start-stop synchronization data transmitting method capable of realizing a stable start-stop synchronization communication even with a clock outputted from an oscillator whose oscillation frequency accuracy is low. SOLUTION: In this start-stop synchronization data transmitting method, a master station is provided with a crystal oscillation circuit corresponding to a baud rate fitting transmission channel characteristics, a slave station is provided with a CR oscillation circuit, the master station transmits a preliminarily defined dummy message in a fixed cycle, and each slave station counts a specific edge time interval of the first bit frame of the dummy message with an output clock from the CR oscillation circuit 109, and generates a baud rate clock calculated from the count value to perform start-stop synchronization communication.
TL;DR: In this article, a method for baud detection in a communication device (700) includes the steps of sorting phase pulses among overlapping sets of time slots, and counting phase pulses within each of the overlapping sets, creating corresponding counter values.
Abstract: A method (500) of baud detection in a communication device (700) includes the steps of sorting phase pulses among overlapping sets of time slots (502) and counting phase pulses within each of the overlapping sets of time slots creating corresponding counter values (504). Then, counter values are compared with predetermined thresholds (506-512), wherein a baud pass condition (570) is met when at least one counter has a counter value exceeding an upper threshold and wherein a counter N/2 positions away has a counter value below a lower threshold. The baud pass condition may he further conditioned on meeting the requirement that at least another counter value falls below a middle threshold.
TL;DR: In this paper, a receiver (100) is used for processing a multi-level FSK signal, comprising a converter (101) for converting the multilevel FSK signals into a sequence of state transitions, and a baud rate detector (111) comprises in a plurality of sampling intervals, wherein each of the sampling intervals is offset by a first predetermined time from other sampling intervals.
Abstract: A receiver (100) is used for processing a multi-level FSK signal, comprising a converter (101) for converting the multi-level FSK signal into a sequence of state transitions, and a baud rate detector (111). The baud rate detector (111) comprises in a plurality of sampling intervals, wherein each of the plurality of sampling intervals is offset by a first predetermined time from other sampling intervals, and wherein each of the plurality of sampling intervals is further subdivided into a plurality of recording intervals, a plurality of counters (502-508) for counting the sequence of state transitions that occur during at least a minimum number of the plurality of recording intervals. The baud rate detector (111) further comprises a baud rate detection circuit (524) for detecting the desired baud rate based on counts recorded in a memory (522).
TL;DR: In this article, a method of compression in accordance with the invention encodes datapoints into relative data with periodically interspersed actual data, encoded in various bytes-codes, each including an identifier to identify the type of data (e.g., relative or actual) the byte-code carries.
Abstract: A method of compression in accordance with the invention encodes datapoints into relative data with periodically interspersed actual data. The data is encoded in various bytes-codes, each including an identifier to identify the type of data (e.g., relative or actual) the byte-code carries. Use of byte-codes avoids interference with the communication channel by avoiding compressed data interpretation as channel control commands. A method in accordance with the invention, when used in a transmission line test system, has resulted in real-time data transfers of data over a 9600 baud network of less than one second.
TL;DR: It is shown that a fractionally-spaced equalizer can handle the intersymbol interference (ISI) induced when the propagation channel does not introduce too much ISI.
Abstract: The improved convergence speed and tracking properties of fractionally-spaced equalizers are analyzed. We consider in particular the effect of a frequency offset between the transmitter baud rate and the receiver sampling clock that induces important time-variations. We show that a fractionally-spaced equalizer can handle the intersymbol interference (ISI) induced when the propagation channel does not introduce too much ISI.
TL;DR: The advantages of using the PETRA in a spacecraft's Data Handling System (DHS) compared to a traditional implementation are introduced.
Abstract: The Packetised Essential Telemetry Retrieval ASIC (PETRA) is a mixed analog/digital chip for retrieving sensor data on-board spacecraft, designed by Silicon Systems Ltd. One single PETRA can connect up to 40 digital and/or analog sensors which are periodically sampled. CCSDS Telemetry packets containing the data are automatically generated and can be delivered directly to the transfer frame generator or to an on-board processor. The packets are output serially, at a nominal baud rate of 9600 bps or 115.2 kbps, with the interface being directly compliant with both the Virtual Channel Multiplexer (VCA) and RS-232 type asynchronous serial interfaces. The PETRA is a 0.8 /spl mu/m double-metal, double-poly CMOS mixed signal device with a die size of 26 mm/sup 2/. The dynamic power dissipation is 80 mW with a static dissipation of 30 mW. This paper introduces the advantages of using the PETRA in a spacecraft's Data Handling System (DHS) compared to a traditional implementation. An overview of the PETRA functionality is presented, followed by a description of the device architecture. An outline of the design methodology is then followed by a discussion of the PETRA demonstration system.
TL;DR: In this paper, a device and method for controlling the baud rate between a portable telephone and an external device is provided, where a first input/output (I/O) port is connected to the portable telephone which transmits and receives data to/from the portable phone, and a second I/O port is attached to the external device, and the data is transmitted and received from the external devices via the second I /O port.
Abstract: A device and method for controlling the baud rate between a portable telephone and an external device is provided. A first input/output (I/O) port is connected to the portable telephone which transmits and receives data to/from the portable telephone, and a second I/O port is connected to the external device which transmits and receives data to/from the external device. A controller interposed between the first and second I/O ports, detects a first baud rate of the portable telephone, converts an initial baud rate of the first I/O port to the first baud rate, and transmits the data to the portable telephone via the first I/O port. The controller also detects a second baud rate of the external device, converts an initial baud rate of the second I/O port to the second baud rate, and transmits the data to the external device via the second I/O port.