Abstract: Careful partitioning of signal-processing tasks between the analog and digital domains to exploit the strengths of each results in an efficient design of a 2B1Q ISDN basic-rate U-interface single-chip transceiver. This 5-V CMOS device provides transmission across the digital subscriber line at 160 kb/s full duplex, in full compliance with ANSI standard T1.601. The serial 2B+D data from the digital interface is rate-adapted to 160 kb/s and cyclic redundancy check (CRC), maintenance, and control bits are inserted in the digital interface (DIF) section of the circuit. The resulting data stream is then scrambled and 18-b synchronization words are inserted. Conversion to an 80-kHz four-level signal takes place in the line encoder. The transmitter includes a 2B1Q pulse shaper, a five-level fully differential pulse-duration-modulation digital-to-analog (PDM D/A) converter, a third-order transmit filter, and a fully differential line driver. A raised-cosine 78% time-roll-off pulse is stored in the pulse shaper, using a PDM code, at 96 samples per baud. Pulse symmetry allows storage of the first half-pulse only. The back half is generated by a time-mirror circuit. At every baud interval, the current di-bit encodes the pulse front half, while the past di-bit encodes the pulse back half. The two resulting quantities are then combined and provided to a 7.68-MHz five-level PDM D/A converter. Undesirable high-frequency components are eliminated by one pole of low-pass filtering in the D/A converter circuit and two extra poles in the line drive circuit. >

Abstract: An apparatus and method for processing a signal is capable of determining the presence or absence of a signal having a predetermined baud rate. By initializing counting registers (131-139) to either first or second values, and receiving the signal, either the presence or abscence of the baud rate may be more rapidly detected. Rapid detection provides for improved battery (20) savings when the invention is used within a portable receiver such as pager. The invention provides for positive detection of the predetermined baud rate while rejecting a baud rate being an integer divisor of the predetermined baud rate. Additionally, as a result of the determination of the presence of the predetermined baud rate, a sample clock may be established for receiving data at the baud rate.

Abstract: A combined BAUD rate generator and digital phase locked loop (DPLL) circuit operates in either an asynchronous BAUD rate generating mode or a synchronous phase-locked mode. The combination circuit requires less circuitry than a functionally equivalent circuit with a separate BAUD rate generator and DPLL. The combination circuit comprises a count register, a period register, a decrementing/incrementing circuit, a phase adjusting circuit, and a clock option register. In a first operating mode, the combination circuit functions as a programmable BAUD rate generator which may be used for asynchronous communication applications. In a second operating mode, the combination circuit functions as both a programmable BAUD rate generator and a digital phase locked loop that may be used for synchronous communication applications and that includes an improved method for phase locking a sampling signal to an input signal. The combination circuit utilizes the same period register, count register, clock option register, and other common circuitry, during both the BAUD rate generating mode and the phase locked mode.

Abstract: In a system including a host, at least one peripheral and a peripheral repeater having a transmitter/receiver for the peripheral, with the peripheral repeater receiving messages from the peripheral and retransmitting them to the host and receiving messages from the host and retransmitting the messages to the peripheral when a change in baud rate is desired, a message is sent from the host to the peripheral, through said peripheral repeater to set a new baud rate, another message is sent from the host to the peripheral repeater to change the baud rate of the transmitter/receiver and the baud rate of the peripheral which was set is maintained in a table in the host.

Abstract: The bit-error-rate performance of the noncoherent quaternary-phase-shift-keying modem scheme in a digital cellular mobile communication system is analyzed. The system is modeled as a frequency-selective fast Rayleigh fading channel corrupted by additive white Gaussian noise and cochannel interference. The demodulation scheme considered is differential or discriminator detection. The probability density function of the phase difference between two consecutive symbols in such a channel is derived. In the pi /4-QPSK system, the information is completely contained in this phase difference. The bit error rate is then calculated by numerical integration. Numerical results show that for the recommended new USA standard system ( pi /4-DQPSK, f/sub c/=850 MHz, symbol rate=24 k Baud), the bit error rate is controlled by the cochannel interference, which is expected to be between 10 and 15 dB. >

Abstract: The viability of a voiceband signal classification technique which can service as a front-end for digital signal interpolation is demonstrated. The technique uses second-order statistical parameters of the complex envelope of the input signal. The input signal is assumed to be in mu -law PCM (pulse code modulation) form. For observation windows of at least 128 ms, it is shown that this method correctly classifies the input baud (e.g. 2400, 1600, 1200, 600 and 300 symbols/s) and modulation type (e.g. QAM, PSK, and FSK). This information allows the determination of the bit rate of most voiceband data signals. Coupled with a digital signal interpolator and variable rate coding, an increased compression ratio on long-haul digital trunks can be achieved. >

Abstract: An innovative digital timing recovery method for synchronous digital receivers is described. This method is based on estimating the impulse response of the channel and then choosing an optimal sampling phase from this estimate. The method uses an adaptive transversal filter (TF), operating at the baud rate and driven by a decision-directed reference, to cancel the sampled received far-end signal. This timing recovery technique connects, in a natural way, with receivers using decision feedback equalizers (DFEs). A 30-tap DFE receiver incorporating this timing recovery scheme has been simulated and implemented in real time on a single DSP (digital signal processor). >

Abstract: A demodulator capable of variable baud rate (f/sub b/) operation satisfies the requirements for a forward error correcting decoder for satellite communication systems such as VSAT systems. A new method of frequency acquisition, called swept automatic frequency control has a wide f/sub b/-independent acquisition range and prevents false locking of the carrier recovery circuit. The authors have evaluated such a demodulator and confirm that it performs satisfactorily. >

Abstract: In order to accomplish the object of the present invention there is provided a network independent clocking (NIC) circuit which allows a local synchronous master to exchange data with a local data adpater. The NIC circuit includes a phase measuring block for continually generating a local phase difference indicator, where the local phase difference indicator indicates a phase relation between the local data adapter and the local synchronous master. The local phase difference indicator is transmitted to a remote data adapter. Back locally, a phase difference indicator is received from a remote data adapter. A baud clock is generated and used to transfer data from the data adapter to the synchronous master, the baud clock generator uses the phase difference indicator to recreate the phase difference between the remote data adaper and the remote synchronous master.

Abstract: Fractional rate modulation is accomplished by separating incoming data into frames of bits. Each frame is partitioned into bit words of unequal lengths. The words are divided by a modulus to obtain remainders. The remainders are transmitted using for example QAM modulation. At the receiving end the process is reversed. The ratio of the baud rate of the system to the incoming bit rate defines the modulus as well as the number of QAM modulation points.

Abstract: For ptI see ibid, vol38, no1, p31-8 (1990) A comparison is made of the transmission performance of various line codes in the subscriber line environment and at a line rate around 260 kb/s The simulated transmission environment includes transhybrid echo, intersymbol interference, and near-end crosstalk from identical digital-subscriber-line transmission systems The simulated transceiver incorporates an echo canceller and a decision-feedback equalizer that are optimal in the minimum-mean-squared-error sense Both the echo canceller and the decision-feedback equalizer have a tap spacing equal to the symbol period The line codes investigated include five block codes that offer reduced baud rates and five codes that do not reduce the baud rate Under the conditions of this study, block codes do show an advantage over nonblock codes, with the 2B1Q block code yielding the best performance >

Abstract: A novel system for concurrently transmitting audio signals and digital codes from an AM radio station to each receiver is presented. Experiments for sending a still picture from the AM radio station to the receiver have been carried out to check whether the present system is satisfactory. Digital codecs were transmitted at a baud rate of 300 b/s with 2- phi to 4- phi phase-shift keying, and the bit and block error rates were on the order of a few percent. >

Abstract: The method synchronises a scanning pulse generator with the pulse sequence of an unknown digital signal. The symbol length of the sequence is first estimated roughly, then, using this estimate together with the original signal, there is formed a pulse sequence with a corresponding pulse frequency for the synchronising process. Two successive lengths are combined into a double length and then by a quantisation process for each double length the number of symbol lengths contained in it is determined. Each double length is manipulated with the original pulse flanks, so that each can be divided into a number of individual steps corresponding with this number of roughly estimated symbol lengths. By a Walsh transformation the maximum of the power intensity spectrum of this individual step or unit pulse sequence is calculated and the frequency corresponding to this maximum is used as the corrected symbol rate in the synchronising process. USE/ADVANTAGE - The method of synchronisation reacts quickly to changes in the baud rate. It is suitable for data communications systems with satellites.

Abstract: PURPOSE:To improve the reliability of a measuring instrument itself and to enlarge universality and an applicable range by coupling a digital transmitter to the analog transmission measuring instrument in the system of an adapter and executing digital transmission with a central unit. CONSTITUTION:A digital transmitter 100 to be fitted to each analog measuring instrument 10 as the adapter transmits a digital signal by using an analog transmission line, which is already provided, and in this case, the transmission line is used as a digital transmission line by separating the analog measuring instrument 10 from the transmission line by a switch 109. By changing over the switch 109, the analog measurement value of the analog measuring instrument is transmitted through a transmission line 1 to a center device 300 and in such a state, when it is desired for the central unit 300 to execute the next digital transmission, a pulse according to a transmission baud rate is superimposed to the transmission line 1. Since only a band for digital transmission is passed through the pulse transformer of the digital transmitter 100 which is fitted to each measuring instrument 10, operation is switched to the digital transmission after it is detected that a digital signal comes. Thus, the universality and applicable range can be enlarged.

Abstract: PURPOSE:To improve the transmission efficiency by using a received error signal or busy signal sent from a receiver side so as to revise the transmission rate. CONSTITUTION:When a data RXD received this time is reception error information sent by an opposite station (reception of a reception error signal), a communication LSI2A outputs an error detection signal 6, and when a baud rate generator 3 upon the receipt of an error detection signal 6 outputs a transmission clock whose frequency (transmission rate) is decreased by a prescribed quantity. Thus, a serial communication equipment upon the receipt of a reception error signal RXD decrease the transmission rate automatically at the next transmission to send a data TXD and a transmission clock TXC and decreases further the transmission rate when the reception error signal RXD is received successively. When no reception error signal RXD is inputted, that is, normal communication is finished, the serial communication equipment increases the transmission rate by a prescribed value each conversely at each transmission time till the transmission rate reaches a prescribed upper limit. Thus, the transmission efficiency is improved.

Abstract: A parallel architecture for an analog implementation of the Viterbi algorithm is presented. The implementation uses mostly continuous-time circuitry to achieve high speed and low complexity. The architecture also allows the designer to reduce the sampling rate required for a given baud rate at the expense of additional circuitry. >

Abstract: A signalling protocol (70) comprising a plurality of interleaved phases (90a, 90b, 90c and 90d) is transmitted at one of a plurality of baud rates, the plurality of baud rates being multiples of a base baud rate. The signalling protocol (70) allows a selective call receiver (FIG. 5) to decode at an operating baud rate equivalent to the base baud rate irrespective of the transmission baud rate by decoding only a portion (90a, 90b, 90c or 90d) of the transmitted signal, the portion decoded (90a, 90b, 90c or 90d) determined by the baud rate and the address of the selective call receiver.

Abstract: Described is a circuit arrangement that aligns the receiver of a communications device with the bit boundaries of a serially received data stream. The circuit arrangement delays a bit in a synchronized data stream and correlates it with a next bit in the data stream. If the bits are equal, a signal is generated to reset a synchronization latch. Thereafter, the receiver is synchronized to the incoming data.

Abstract: A baud-rate full-duplex digital transmission unit for 144-kb/s basic access over an existing subscriber loop plant is described. The adaptive operations performed include echo cancellation, decision feedback equalization, reference control, and timing recovery. The unit operates at the baud rate, allows a fully digital implementation, and requires no special training sequences. Baud-rate timing recovery is a crucial issue. A method which only estimates timing error when certain data sequences occur is described and applied to subscriber loops. The behavior of this method in a region of incorrect decisions due to intersymbol interference is analyzed as a one-dimensional random walk. This indicates that escape from this region will be rapid when the gain is moderately large. Timing issues at exchange and subscriber ends are discussed. Different start-up strategies involving staggered turn-on plus gear shifting for both ends are proposed to decouple the adaptive loops and yield relatively low convergence times. In particular, at the exchange end, timing recovery is initially decoupled by successively adapting the remaining loops at several instants within the baud period. The instant closest to the optimum is then that instant with a minimum timing estimate variance. >

Abstract: PURPOSE: To make the detector small and to attain low power consumption by extracting a line spectrum component directly and detecting the timing of a reception signal based on the extracted line spectrum component. CONSTITUTION: A line spectrum of a baud rate component is included in one of two orthogonal signals being a π/4 shift (D) QPSK delay output and the line spectrum component is synchronously with the transmission clock. The recovery of a recovered clock is implemented by passing an output having the line spectrum in a baud rate frequency in two signals outputted from a delay detection circuit 17 through a narrow band pass filter having its pass band in the baud rate frequency. That is, since the line spectrum of the baud rate component is synchronously with the transmission clock, a recovered clock not including noise or the like to the utmost is generated by extracting the line spectrum component. COPYRIGHT: (C)1992,JPO&Japio

Abstract: PURPOSE:To easily and speedily execute a setting work without excessive parts and space by automatically setting a Baud rate which is coincident with a communication opposite based on the analysis of a reception code at the time of receiving a prescribed code at first from the communication opposite CONSTITUTION:An arithmetic control unit 15 decides the presence or absence of a communication input from the communication opposite At the time of YES, a pulse width measurement circuit 20 measure the pulse width tw of the prescribed code which has initially been received and the measurement value is fetched into the arithmetic control unit 15 The unit 15 decides whether the measurement value tw shows either tw>=56ms or 28<=tw<56ms, or either 14<=tw<28ms or tw<14ms If a decision is YES, a frequency division rate of a frequency divider 17 is set so that the Baud rate shows 600bps Data transmission by the set Baud rate is executed

Abstract: PURPOSE:To eliminate the need for the manual setting of a parameter by sending a specific character from the sender side so as to inform a baud rate and a data format at the sender side to the receiver in advance and matching them from the sender side with those of the receiver automatically CONSTITUTION:A sender side sends it that a character sent next is a specific character for detecting a parameter with a break signal to a receiver side The receiver side uses a timer of a CPU to count a pulse width of 'L' when a start bit 1 comes from the sender side The receiver side decides the baud rate of the sender side depending on the numeral In the case of detecting the data format, the data of the succeeding one bit is read by the CPU at the receiver side after a time x/2 from a point of time 3 when the level reaches 'L' again Then the data format is decided from the read data Thus, the communication parameter comprising the band rate and the data format is detected automatically Thus, it is not required to set the communication parameter manually

Abstract: A modem implementation a high data transmission rate is implemented by means of pulse width modulation. The timing magnitude for each baud is weighted by the binary value of the data input. Minimal components are employed and the entire circuit is comprised of digital components except for a few analog components including a comparator for detecting transitions in the received pulse width modulation signal. This modem is particularly applicable to digital transmission of a digital video picture data via telephone lines to implement a video telephone. The video picture along with the synchronization signals from a video source are digitized and stored in a memory. The video telephone operates by sending and receiving by pulse width modulation both the video data and the synchronization signals. The inverse of the video is entered into a binary counter in the modem and the pulse width is the result of counting to a transition of a more significant bit of the counter to create a pulse width modulation transmission on the telephone lines. On receiving pulse width modulation video the binaray counter is loaded with all ones and counted up until a transition of the received state is detected. Then the counter is read to recover the sent data. Provisions are included to adjust for received pulse widths longer or shorter than expected. The data from the video source or the received video can be displayed on a local monitor.

Abstract: PURPOSE:To realize low power consumption and to improve the reliability by generating simultaneously a clock for baud rate and a clock for real time clock from one clock generator. CONSTITUTION:Clocks for baud rate of 19200Hz, 9600Hz, 4800Hz, 2400Hz and 1200Hz are obtained by a baud rate clock generating section 2 composed of a 1/2 frequency division stage circuit from, e.g., the clock generator 1 of 38.4kHz. A clock output in 1200Hz from the baud rate clock generating section 2 is given to a real time clock generating section 3 composed of a 1/2 frequency dividing circuit, a 1/5 frequency dividing circuit and a 1/3 frequency dividing circuit, the frequency of 75Hz is obtained from the 1200Hz clock by the 1/2 frequency dividing circuit and divided into 3Hz while passing through twice the 1/5 frequency dividing circuit and the 3Hz frequency is given to the 1/3 frequency dividing circuit and divided into a 1Hz real time clock.

Abstract: A modem with an improved digital signal processor is described A first processor (l2) controls the overall operation of the modem and communicates with an external device (not shown) through a connector (l0) A second processor (34) performs signal processing on both transmitted and received data signals in a manner which saves both time and memory space The processes which are described comprise a 240 bit per second handshake signal detector, a fast linear-to-mu lay converter the transmitter signal generator, a fast-acting nonlinear automatic gain control, a jitter-free transmitter phase-locked loop, a baud clock timing recovery circuit, and a phase and amplitude modulator Also described is a protocol; for exchanging data between the processors (l2) (34) A logic gate array (l5) allows thee processors (l2) (34) to communicate with each other and also performs other functions Therefore, each of the processors (l2) (34) performs the operations for which it is most suited by its design

Abstract: PURPOSE: To make a structure suitable to be IC by providing a pulse waveform shaping device which converts digital data into a prescribed pulse shaping wave and using a switching capacitor pulse shaping device instead of a filter which continuously operates. CONSTITUTION: A digital input signal that consists of two parallel bits per baud is received by an input line 12, given to an input of a shift register 13, and the register 13 is serially connected to another shift register 14. These two registers 13 and 14 are clocked by their respective clock sources CK1 and CK2. Parallel outputs of the registers 13 and 14 are added to switching capacitor pulse wave shaping devices 10 and 11 respectively. Outputs of the devices 10 and 11 are added to each other by an adder 15, and an output of the adder 15 is added to an input of a coarse low-pass filter 16. A synthesized output signal is outputted from an output line 17 of the filter 16.

Abstract: In this paper we describe communications between a personal computer and any instrument with a serial port for the purpose of collecting data or controlling equipment and a program for performing this task. From a user-defined file, the software reads the communication parameters: baud rate, data bits, stop bits and parity. The communication protocol is also read: echo, acknowledge and end-of-transmission characters. The software can be used to determine the protocol, to check the integrity of the communications, and can form the basis of a program for more specific applications.

Abstract: The total costs of online searching in four hosts — Data‐Star, Dialog, ESA‐IRS, and STN International — were evaluated in a study conducted at the Information Service of the Technical Research Centre of Finland. To make the comparison as comprehensive as possible, six databases were used, all of which are available in the four hosts. The databases were BIOSIS, Chemical Abstracts, COMPENDEX, FSTA, INSPEC, and NTIS. The costs were analysed separately for the searching phase and for the output phase. For the searching phase, the costs were calculated as a function of the connect time. For the output phase, the cost per displayed record were estimated. The estimates were based on measured output time. The telecommunication costs were included, but their share is shown separately. The effect of transmission rate on the connect time and telecommunication costs was also studied by using two different speeds, 1200 baud and 2400 baud. The results of the study are presented in graphs and in tables. The graphs show the conducted values of the various cost components (connect time, output, telecommunication) for the four hosts and six databases. The comparisons of total costs for various types of online searches are presented in tables. At 1200 baud, the most economic searches are usually made in ESA‐IRS. Data‐Star, Dialog and STN are competitive only in very short searches, and at rather high levels of output. At 2400 baud, the competitiveness of Data‐Star, Dialog and STN is much better, especially if a medium‐length format is used for output. Data‐Star and STN which do not have a data network of their own suffer from higher telecommunication costs.

Abstract: Abstmct- In designing DSL (digital subscriber line) transceivers to support ISDN (integrated services digital network) Basic Access, a key issue is the choice of proper line codes. This paper reports a study to understand and compare the transmission performance of various line codes in the subscriber line environment and at a line rate around 160 kbitsk. The study is carried out by way of computation. The simulated transmission environment includes transhybrid echo, intersymbol interference, and near-end crosstalk from identical DSL transmission systems. The simulated transceiver incorporates an echo canceller and a decision-feedback equalizer which are optimal in the minimum meansquared error sense as discussed in Part 1 [l]. Both the echo canceller and the decision-feedback equalizer have a tap spacing equal to the symbol period. The line codes investigated include five Mock codes which offer reduced baudrates and five other codes which do not reduce the baudrate. Under the conditions of this study, Mock codes do show advantage over nonblock codes, with the 2BlQ, a Mock code, yielding the best performance.