Abstract: An interface for installation in a printer housing, to provide an adaptable connection between the printer and any of a variety of computers and to allow the printer- interface combination to emulate any of a number of different printers having different protocols for printer control codes. The interface can be conveniently switched, either manually or under computer control, to adapt to a different control code protocol, to select one of several different standards for digital data transfer, to select a different baud rate for receiving serial data, or to adapt automatically to a transmission baud rate. Manual switches also permit reversal of the polarity of selected signals used in the transmission of data, to adapt to the conventions used in a selected computer. The interface also optionally performs or initiates a number of print formatting control functions.

Abstract: Digital data is transmitted over AC power lines at typically a 300 baud rate and at a frequency of 130 kilohertz representing a binary ONE and 131 kilohertz representing a binary ZERO. Apparatus in the receiver relay including a quadrature detector converts the high frequency signals to digital binary signals which are applied to a microprocessor. The microprocessor generates signals to control relays in accordance with the information received from the AC power lines.

Abstract: A line adapter system for handling byte-oriented data transfers between remote data terminals and I/O subsystem. Working in conjunction with a controlling microprocessor, the line adapter provides input output means for regulating the baud rate of transmission to/from a remote terminal and for the timing and protocols required for both synchronous and asynchronous data transmission. The microprocessor may address and control various of the timing elements and byte to bit transfer means of the input/output circuit means. Likewise, each of the elements of the input/output circuit means may request service from the microprocessor for further detailed instructions.

Abstract: A 14.4 kilobit/second modem uses an encoding scheme in which groups of five bits are encoded as one of thirty-two (2 5 ) possible code groups. This is done by using quadrature amplitude modulation and a 6 by 6 space-state constellation which allows a maximum of thirty-six different points to be encoded. Since only thirty-two points are needed the four outer corner points of the constellation are not used. In order to achieve the desired 14.4 KBPS data rate the baud clock must run at 2880 Hz. However, this bandwidth is very close to the maximum bandwidth available on voice-grade telephone lines. Accordingly, data encoding and data recovery techniques must be used which maximize the probabilities of correctly receiving the encoded data signals. These techniques include (1) data scrambling/descrambling; (2) assigning groups of five bits to constellation points, including performing rotational and Gray encoding; (3) a baud clock recovery scheme at the receiver which is performed prior to partial response encoding; and (4) a start-up technique using a three-level partial response ideal reference sequence during initial training at the receiver. In addition, the invention uses passband equalization, class I partial response encoding accomplished by the passband equalizer, and independent inphase and quadrature Viterbi decoders at the receiver.

Abstract: In a QPSK system using one cycle of a squared-off sinusoid per Baud period to represent the data dibits, the following are disclosed: (1) a direct detection circuit using samples taken only during the second and third quarters of the Baud period; (2) timing recovery by recognition of the opposite polarity of any QPSK signal compared to a half-Baud-delayed version of itself; and (3) an encoding scheme wherein only one of the two dibits is differentially encoded

Abstract: The paper describes a near-maximum-likelihood detection process suitable for use in a synchronous serial digital data transmission system that operates at 9600 bit/s over an HF radio link. The data signal at the input and output of the HF radio link is here a 2400 baud 16-level QAM signal with a bandwidth (measured between the 6 dB points) from about 600 to 3000 Hz. The detector is a development of a technique that operates at 2400 bit/s with a four-level QAM signal and which itself originated from a reduced-state Viterbi-algorithm detector. Results of computer simulation tests are presented, showing the tolerance to additive white Gaussian noise of a 9600 bit/s data transmission system employing the new detector and operating over a model of an I-IF radio link. The latter has two independent Rayleigh fading sky waves that introduce frequency spreads of 0.5 or 2 Hz into the data signal and have a relative transmission delay of 1 or 3 ms. It is assumed that the correct estimation of the channel is achieved at the receiver.

Abstract: Apparatus, and a related method, for fast carrier acquisition in a modem. The apparatus includes circuitry to speed carrier acquisition by the determination of which of two alternate phasors is being received during a baud synchronization period of a signal preamble before data transmission. Another aspect of the invention involves the use of a complex matched filter for the determination of the start of an equalizer training sequence in the signal preamble. The output of the matched filter exhibits a deep null at the start of the training sequence, since the beginning of the sequence bears an inverse relationship to the end of the preceeding baud synchronization period

Abstract: A 4800 bit-per-second full duplex modem is described which utilizes the full bandwidth of ordinarily available dial-up telephone circuits for transmission of data in both directions in different pass-band portions thereof. The two pass-bands overlap in about the middle of the telephone band in order to fully utilize that bandwidth for high speed data transmission. The overlap is less than that which will cause a greater error rate than desired from remote echos of transmitted data. Local echos, which are much stronger, resulting from the overlap bandwidth portion are cancelled by an echo cancelling technique. Local echo cancelling is accomplished at the baud rate, generated in each modem, for substraction from a received signal; a cancellation signal is generated from a time varying system that depends upon the modulating and demodulating carrier signals.

Abstract: PURPOSE:To decrease the number of interruptions to stations where no data link is established and to improve the processing ability, by making a Baud rate for data link establishment and the Baud rate for actual data transfer to have a different value from each other. CONSTITUTION:When a station 1 transmits data to a station 3, a packet for data link establishment is transmitted to the station 3 in the Baud rate of low speed. After the station 3 returns the response for confirmation to the station 1, the station 3 designates that the succeeding data transfer is executed in the Baud rate of high speed to a network controller 6. On the other hand, a network controller 5 of a station 2 independently of the data link establishment is in the Baud rate mode of low speed, then the data transfer packet executed in the Baud rate of the said high speed is not correctly received, allowing to avoid useless interrupting processing to the station 2.

Abstract: PURPOSE:To simplify a circuit constitution and to reduce the area of a board for a device using a programmable timer, by facilitating the setting of the baud rate with a change of software. CONSTITUTION:A microprocessor 2 changes the initial set value of a register in a programmable timer module 1 on the basis of the software stored in a memory 3. As a result, it is possible to deliver a signal phiout which is obtained by dividing an enable signal phiE or clock signal phiC down to an appropriate frequency. This signal phiout is used for a serial I/O interface 5 as a data transfer signal between an input/output device 6 and the interface 5. This facilitates the setting of the baud rate with a change of the software. As a result, the circuit constitution is simplified with a reduced board area.

Abstract: PURPOSE:To reduce phase lock-in time of a sampling phase synchronism circuit, by constituting a sampling phase error detection circuit on which stable points of the sampling phase can produce a plurality of phase error signals between the phase angles of the baud rate section of a received analog signal. CONSTITUTION:A received analog signal of a base band obtained at a reception section of an MODEM is sampled with a sampling pulse 14 at an A/D conversion circuit 13 and inputted to a sampling phase error circuit 14. The input signal is filtered at a band pass filter 20 consisting of a half the baud rate, squared at a multiplier 21 in the circuit 16, and then filtered at a band pass filter the same as the baud rate and inputted to phase comparators 23 and 24. Since and cosine reference signals are applied to the comparators 23, 24 from an oscillation circuit 19, a phase error signal S7 of sin(2DELTAphi) appears an output of a multiplier 25 to control the phase of the oscillator 19.

Abstract: The system consists of at least two transmitting/receiving units (1;4). A transmitting part (9) contains a transmitter modulator and a coder. In the case of a "1" bit to be transmitted, the logic level of the state of a modulation signal preceding in time is reversed at the modulation input of the transmitter modulator and, on the other hand, it remains unchanged in the case of a "0" bit to be transmitted. In the transmitter modulator, a phase reversal by 180 DEG of the carrier pulse frequency is carried out, depending on whether a "1" bit or a "0" bit is present at the modulation input of the transmitter modulator. A receive part (10) contains a combined decoder/ demodulator, while a bit-clock and a shift-clock signal are produced in a clock generator (8). A common power supply part (11) is used both for transmitting as well as for receiving.