Abstract: In this paper, a serial port based debugging tool for the Arduino platform is presented. The tool is based on a modification of the Arduino IDE (Integrated Development Environment) and libraries. It includes the basic options of debugging tools (stepping, breakpoints, variable inspection, etc.) without the need of a hardware debugging interface. The tool has been designed taking into account that is going to be used by beginners or intermediate users, which is the most common profile among Arduino users. The tool tries to promote debugging procedures that are not based on trial and error, and contributes to the Arduino environment with another teaching resource.

Abstract: In an embodiment, a debug architecture for a processor/System on Chip (SoC) etc., includes a central debug unit to receive one or more functional debug signals, the central debug unit further configured to receive debug information from at least one firmware source, at least one software source, and at least one hardware source, and to output compressed debug information; a system trace module to receive the compressed debug information and to time stamp the compressed debug information; a parallel trace interface to receive the time stamped compressed debug information and to parallelize the time stamped compressed debug information; and an output unit to output the parallelized time stamped compressed debug information on one of a plurality of output paths. Other embodiments are described and claimed.

Abstract: In accordance with an embodiment, described herein is a system and method for dynamic debugging in an application server environment. An exemplary method can provide, at one or more computers, including an application server environment executing thereon, a plurality of deployable resources which can be used within the application server environment, one or more running managed servers, the one or more managed servers being within a domain, and a debug framework, the debug framework comprising a debug patch directory, the debug patch directory containing one or more debug patches. The method can activate a selected debug patch within the domain, the selected debug patch comprising at least one class, the selected debug patch designed to gather information about the problem within the domain. The managed servers, upon activation of the selected debug patch, can remain running. The method can also deactivate the selected debug patch without requiring a restart.

Abstract: Embodiments of an invention for protecting information processing system secrets from debug attacks are disclosed. In one embodiment, a processor includes storage, a debug unit, and a test access port. The debug unit is to receive a policy from a debug aggregator. The policy is based on a value of a first fuse and has a production mode corresponding to a production value of the first fuse and a debug mode corresponding to a debug value of the fuse. The test access port is to provide access to the storage using a debug command in the debug mode and to prevent access to the storage using the debug command in the production mode.

Abstract: Debugging is challenging and labor-intensive Debugging programs with weak or no oracle is even more difficult due to lack of passing and failing test runs as well as their comparisons To address these challenges, we exploit metamorphic relations to construct new programs that are enhanced with synthesized oracle, and combine concolic testing and branch-switching debugging to localize potentially faulty places in original programs We name our approach concolic metamorphic debugging (or Comedy for short) We experimentally evaluated Comedy with real-world Java programs The experimental results reported that Comedy successfully generated debugging report for 884% of 2,330 faulty programs The average branch distance between the reported locations and the real fault places is only 168 Besides, 36% of the debugging reports precisely locate the fault

Abstract: This work tackles the conflict between security and debugging of modern Systems-on-Chip (SoC). On one hand, security objectives require confidentiality of assets such as cryptographic keys, configuration and calibration data, and proprietary firmware. On the other hand, debugging instrumentation enables tracing of internal SoC signals that expose these assets via a debug port or debug memory. Mechanisms proposed to tackle this conflict either disable debugging before the SoC is released, or provide binary (all-or-nothing) access to the debugging instrumentation based on an authentication mechanism. The first approach is not practical because the debugging instrumentation is needed for in-field maintenance. The second approach does not protect against a rogue insider in a debugging team. We enhance the debugging instrumentation with security features to ensure that assets are only exposed to their owners during debug. The features first tag each asset with a unique ID of its owner, authenticate each debugger to verify access privileges, and filter the assets to determine which ones to expose given the debugger privileges. The proposed features incur 6% area and power costs, and do not impact firmware execution during debug.

Abstract: Debugging of device drivers' failures is a very tough task because of kernel panics, blue screens of death, hardware volatility, long periods of time required to expose the bug, perturbation of the drivers by the debugger, and non-determinism of multi-threaded environment. This paper shows how reverse debugging reduces the influence of these factors to the process of drivers debugging. We present reverse debugger as a practical tool, which was tested for i386, x86-64, and ARM platforms, for Windows and Linux guest operating systems. We show that our tool incurs very low overhead (about 10%), which allows using it for debugging of the time sensitive applications. The paper also presents the case study which demonstrates reverse debugging of the USB kernel drivers for Linux.

Abstract: Remote debugging facilities are a technical necessity for devices that lack appropriate input/output interfaces (display, keyboard, mouse) for program- ming (e.g., smartphones, mobile robots) or are simply unreachable for local development (e.g., cloud-servers). Yet remote debugging solutions can prove awkward to use due to re-deployments. Empirical studies show us that on aver- age 10.5 minutes per coding hour (over five 40-hour work weeks per year) are spent for re-deploying applications (including re-deployments during debugging). Moreover current solutions lack facilities that would otherwise be available in a local setting because it is difficult to reproduce them remotely. Our work identifies three desirable properties that a remote debugging solution should exhibit, namely: run-time evolution, semantic instrumentation and adaptable distribution. Given these properties we propose and validate Mercury, a remote debugging model based on reflection. Mercury supports run-time evolution through a causally connected remote meta-level, semantic instrumentation through the reification of the underlying execution environment and adaptable distribution through a modular architecture of the debugging middleware.

Abstract: C-based High Level Synthesis (HLS)-compatible ciruit descriptions from the CHStone benchmark suite are instrumented for debugging purposes using a source-to-source compiler. The debug instrumentation connects C expressions to top-level ports that can be observed during the debugging process. Approximately 50,000 different experiments are conducted to determine the impact on the final circuit caused by the debug instrumentation. Experimental data indicate initial feasibility of the instrumentation approach; all assignment expressions in a program can be instrumented for an average increase in LUT count of about 24%. Increases in FF count and clock period were in the range of 5% to 10%.

Abstract: Embedded Universal Serial Bus (USB) debug (EUD) for multi-interfaced debugging in electronic systems are disclosed. Electronic systems contain complex integrated circuits (ICs) that require extensive testing and debugging to ensure good quality and performance. In exemplary aspects, an EUD is provided in an electronic system. The EUD is configured to send control information to and/or collect debugging information from multiple internal debugging interfaces in the electronic system. The EUD is also configured to convert the debugging information into a USB format so that the debugging information can be externally accessed through a USB interface provided by the electronic system. The EUD can provide non-invasive monitoring of the electronic system. The electronic system is able to use a USB port for communications in a mission mode while EUD is enabled. Additionally, the electronic system can turn on or off all system clocks during power-saving mode while the EUD continues to function.

Abstract: An apparatus and a method for maximizing debugging performance and reducing memory overhead are provided. The method includes generating a debug protocol packet and transmitting the generated debug protocol packet to a diagnostic device. The debug protocol packet includes reference information for at least one string associated with a debug trace.

Abstract: Debugging is a critical step in the development of any parallel program. However, the traditional interactive debugging model, where users manually step through code and inspect their application, does not scale well even for current supercomputers due its centralized nature. While lightweight debugging models, which have been proposed as an alternative, scale well, they can currently only debug a subset of bug classes. We therefore propose a new model, which we call prescriptive debugging, to fill this gap between these two approaches. This user-guided model allows programmers to express and test their debugging intuition in a way that helps to reduce the error space. Based on this debugging model we introduce a prototype implementation embodying this model, the DySectAPI, allowing programmers to construct probe trees for automatic, event-driven debugging at scale. In this paper we introduce the concepts behind DySectAPI and, using both experimental results and analytical modelling, we show that the DySectAPI implementation can run with a low overhead on current systems. We achieve a logarithmic scaling of the prototype and show predictions that even for a large system the overhead of the prescriptive debugging model will be small.

Abstract: Described herein are various embodiments of computer-implemented tools, systems, and methods for managing debugging of different portions of an application (e.g., front-end and back-end) with different respective debuggers in a manner that facilitates debugging the entire application from within the user interface associated with one of the debuggers (e.g., from within a browser interface). In some embodiments, a debug manager acts as a bridge between a web-browser debugger and a back-end debugger, allowing an application developer to debug web applications without leaving the browser.

Abstract: The aim of this paper is to prove the generic nature of a framework used for deployment, debugging and control of DSP applications. The central part of the framework is a debug proxy server with a target independent debug interface. We present an expansion of the proxy server to support debugging applications on a server-based virtual platform by using the same debug interface.

Abstract: In one general aspect, a method can include receiving at least one set of correction instructions, validating the at least one set of correction instructions for use by a debugger when debugging an application program, and generating a debug script. The debug script can include text for automatically implementing the validated at least one set of correction instructions in the debugger when debugging an application program. The method can further include generating a plurality of data structures for use by the debug script based on the validated at least one set of correction instructions, and outputting the debug script to the debugger for use by the debugger when debugging the application program.

Abstract: The breakpoint-based silicon debug approach allows users to stop the normal (system) operations of the circuits under debug (CUDs), extract the internal states of the CUDs for examination, and then resume the normal operations for further debugging. However, most previous work on this approach adopts the transaction-level or handshake-level of granularity, i.e., the CUDs can be stopped only when a transaction or a handshake operation is completed. The granulations at these levels are often too coarse when a transaction or a handshake operation requires a large number of cycles to complete. In this paper, we present a novel debug mechanism, called the Protocol Agency Mechanism (PAM), which allows the breakpoint-based debug technique to be applied at the cycle- level granularity. The PAM can deal with transaction invalidation as well as protocol violation that may occur when a system is stopped and resumed. Experimental results show that the area overhead of the PAM is quite small and the performance impact on the system is negligible.

Abstract: An integrated circuit (IC) having a bridge for interfacing a debugger and method of operating the same is provided In one embodiment, an IC includes a debug control circuit and a debug interface block (DIB) implemented thereon The DIB is coupled to the debug control circuit The IC also includes an interface for a debugger and a number of interfaces for external circuits, each of the interfaces being coupled to the debug control circuit The debug control circuit may function as a bridge for coupling an external debugger to the DIB and to external circuits coupled to the IC through corresponding ones of the interfaces The debug control circuit may establish a connection between the debugger and one of the external circuits Communications between the debugger and the external circuit may be conducted while bypassing the DIB

Abstract: Design verification and debugging with both software and hardware is ever challenging for many-core systems. We present the embedded tracer architecture for application-level communication. Not only can the trace information be optimized, but also the verification can be performed at the system level efficiently. The unified architecture consolidates the debugging flow at different abstraction levels, and facilitates the performance analysis of the entire system as well. The use-case study and experiments have justified the effectiveness of the proposed tracer architecture.

Abstract: An arrangement for disabling a configuration of a first programmable hardware component, having the first programmable hardware component, a second programmable hardware component, and a switching element. The first programmable hardware component has a configuration interface for configuring a logic of the first programmable hardware component, a data interface for communication of the logic with the second programmable hardware component, a debugging interface for debugging and configuring the logic, and a configuration monitoring interface for signaling a configuration process of the logic. The switching element is designed and connected to the debugging interface such that access to the debugging interface during a configuration process of the logic can be disabled.

Abstract: Currently, the JTAG debugging is the most popular technology in the embedded ARM system. After providing a perfect JTAG debug method based on the GPIO pins of ARM chip, the paper analyzed the inner technology by which JTAG standard was accomplished. At last, the focus has been put on the analyses of the Boundary-Scan Chain working processes.

Abstract: A debugging circuit including: a storage configured to store a first code value which is calculated by an encoding method in which a value is changed according to a sequence of a signal in a debugging target circuit, and indicates a stop condition of the debugging target circuit; a code value calculator configured to calculate a second code value by the encoding method based on the signal each time when the signal is changed; and an operation stopper configured to stop an operation of the debugging target circuit when the first code value and the second code value are identical to each other.

Abstract: Due to the increased complexity of modern embedded systems and time-to-market constraints, a debugger with efficient debugging functions is becoming increasingly necessary, and it plays an important role in the development of application systems. Accordingly, the implementation of efficient debug functionalities must a critical process in the design of a new processor. Since deeply embedded processor cores in a core-based system chip allow only restricted access for debugging its internal status, most recent processors employ the on-chip-based debug method that embeds special logic-supporting debug capabilities. In this paper, we propose an on-chip debug support logic that can be embedded into the processor core to support debug functions. Moreover, we describe an overall implementation method of the on-chip-based processor debugger based on the on-chip debug support logic, which includes a source-level debugger and an interface block. We designed an on-chip debug support logic, and embedded it into a target processor core. We used the GNU Project debugger (GDB) as the source-level debugger of the target processor core. An interface block that uses the remote debugging features of GDB was also developed and that includes a software module and a hardware board. We discuss all major design steps for implementing this on-chip-based processor debugger. We have successfully applied the proposed implementation method to develop the processor debugger for two new 32-bit RISC processors. In addition, we introduce another use of the on-chip-based processor debugger in the design of a processor-based system chip, which can facilitate simulation-based functional verification.

Abstract: Electronic companies are increasingly using field-programmable gate arrays in various domains such as application acceleration, complex digital designs or ASIC prototyping. The Verification phase holds a significant place in the FPGA design development process. A key challenge during verification is observability. This is defined as the ability to view all internal states of a circuit. Due to poor observability, a significant portion of designer's effort is spent in this phase, specifically performing the debugging task. A common solution to improve observability is using embedded logic analyzers (ELA) that inserts trace-buffers into the design to record on-chip signal values. When on-chip memory is used for observation it is termed as trace-buffers. This approach has limitations such as slow debug cycles, pre-determining the signals to be traced or using logic resources on FPGA. This work proposes a new debug system for improving the observability while overcoming the limitations of ELAs. The proposed debug system extends a recent technique referred as virtual overlay network (VON) for commercial FPGA device. This network can be perceived as built on top of initial circuit mapping and multiplexes all circuit signals to the on-chip memory for observation. It overcomes the limitation of commercial debug tools based on ELAs. We investigate the factors that inuence the performance of VON for Xilinx Virtex, as it constitutes the core of debug system. We demonstrate that a new bit-stream to program the FPGA connecting hundreds of signals to the on-chip memory can be generated in less than 630 seconds, during debug cycle, for a fairly large circuit having normal re-compilation time of more than 5 hours. The proposed system proves to be a promising way of improving observability and potentially reducing the debug turn time with zero area overhead. Currently, the system is limited to work with Xilinx Virtex family of devices.

Abstract: Debugging in large-scale parallel applications with long runtime where frequency of errors is high became very problematic. Traditional debugging techniques with locating exactly errors no longer seems to be appropriate when applying to these applications because of high overhead in storing trace files, especially they are difficult to be able to scale efficiently. An effective solution to these problems is proposed in loop-based unusual behaviors detecting technique which is capable of defining leaked messages in loops and thus, helps to warn programmers about potential errors to prevent unexpected problems. The proposed technique consists of three order rules suggested to be implemented on high performance computing systems.

Abstract: Embodiments generally relate to a universal debug design which involves integrating a debug controller and a debug card with display together into a single debug design. Debug codes, such as power-on self-test (POST) codes and other error codes, are generated by various subsystems of a server-related system. The codes are transmitted to a controller, which stores the codes in memory. In some embodiments, a multiplexer outputs one debug code from the multitude of received codes, based on a user or event selecting which desired debug code should be displayed. In some embodiments, a decoder converts and sends the LED display signals to a debug card, which displays the debug code on a 7-segment LED display.

Abstract: When testing embedded software in real world operation, remaining failures which have not been detected during unit or system testing can often be observed. The execution of these failures is traced during operation tests of the integrated embedded system to replay it for offline debugging in the laboratory. It is time-consuming to detect the root-causes of noncrashing failures in the replay manually. Dynamic analyses during replay assist the developers in fixing these failures. The implementation of dynamic analyses using standard debugging tools improves the portability to different embedded platforms. Unfortunately, fine-grained dynamic analyses with debugger tools are often not applicable in practice because they require too much runtime effort for monitoring. Our approach accelerates the analyses by monitoring in detail only the locations which are relevant for the failure. It starts with fast monitoring of method calls to detect the approximate location of the failure in the replayed execution. Afterwards, in additional replays, it detects the root-causes by monitoring in detail only the relevant executions of methods. This paper shows how our multi-level concept makes fault localization for embedded software using debugger tools applicable in practice.

Abstract: Systems, apparatuses and methods may provide for receiving one or more debug communications and programming, via a bus, a set of debug registers with debug information corresponding to the one or more debug communications. Additionally, tunnel logic hardware may be instructed to transfer the debug information from the set of debug registers to one or more test access ports of an intelligent device such as a non-volatile memory storage unit having a microcontroller. In one example, if it is detected that debug permission has been granted during a boot process, a control status register may be unlocked. If, on the other hand, the debug permission is not detected during the boot process, the control status register may be locked. Accordingly, an enable bit of the control status register may be used to activate the tunnel logic hardware only if the control status register is unlocked.

Abstract: Multicore architectures represent a complex challenge for software simulators, which may suffer from fidelity loss and long execution times. FPGAs can simulate multicore architectures with scalable performance and high accuracy, but the difficulty of debugging could hinder their adoption. In this paper we propose several techniques for inspection, debugging and verification of multicore architectures, both for software-based and FPGA-based simulations. These debugging extensions are cycle-accurate and non-obtrusive. As a proof of concept, we have developed a 24-core RISC multiprocessor that runs the Linux Kernel, for which we provide three simulation modes: a fast, functional mode, a detailed, cycle-accurate mode, and an FPGA-based mode.

Abstract: Virtual Platforms (VPs) are advantageous to develop and debug complex software for multi- and many-processor systems-on-chip (MPSoCs). VPs provide unrivalled controllability and visibility of the target, which can be exploited to examine bugs that cannot be reproduced easily in real hardware. However, VPs as used for debugging provide only traditional interfaces, such as step-based debuggers and traces, that do little to help with the enormous complexity of MPSoCs and their parallel software. Finding a bug is still largely left to the developer's experience and intuition, using manual means rather than automated solutions. To bridge this gap, this paper presents a novel VP debug visualization and control framework for concurrent software that allows examining and steering the target by means of an abstract representation of its inter-task interactions. Our framework reduces the effort required to understand complex concurrency patterns and helps to expose bugs.