Abstract: Development of wireless sensor network applications remains a challenge, due to lack of visibility into the global network state. Debugging instrumentation using printf-like instructions affects the execution timing and non-intrusive approaches, such as JTAG, have not been used beyond a single node due to their high cost.This paper presents Minerva, a testbed architecture for distributed debugging of wireless sensor networks. At the core of our architecture is a flexible debug board installed at each node. The board design is driven by cost-efficiency of the testbed instrumentation and provides access to the on-chip debug port of the sensor node's processor. We focus on three main debugging modalities: (i) non-intrusive network-wide tracing of the internal state of individual nodes; (ii) synchronous stopping of the whole network on a breakpoint; and (iii) distributed assertion checking. We demonstrate the debugging capabilities of Minerva in use-cases based on well-known sensor network protocols in a 20-nodes indoor testbed. Our results indicate that Minerva provides non-intrusive, network-wide debugging of sensor network applications at a low cost.

Abstract: The present disclosure describes methods, systems, and computer program products for providing remote debugging of a cloud application across a wide area network. A method includes transmitting, from a remote communication device to a cloud computing device, instructions to adjust a running application to a debugging mode; receiving, at the remote communication device from a server coupled to the cloud, aggregated thread data in a data packet by using a second debugging data protocol different from the Java Debug Wire Protocol; receiving a debugging command and applying the debugging command to the cloud application running in the debugging mode.

Abstract: One of the hardest aspects of embedded software development is that of debugging, especially when faulty behavior is observed at the production or deployment stage. Non-intrusive observation of the system's behavior is often insufficient to infer the cause of the problem and identify and fix the bug. In this work, we present a novel approach for non-intrusive program tracing aimed at assisting developers in the task of debugging embedded systems at deployment or production stage, where standard debugging tools are usually no longer available. The technique is rooted in cryptography, in particular the area of side-channel attacks. Our proposed technique expands the scope of these cryptographic techniques so that we recover the sequence of operations from power consumption observations (power traces). To this end, we use digital signal processing techniques (in particular, spectral analysis) combined with pattern recognition techniques to determine blocks of source code being executed given the observed power trace. One of the important highlights of our contribution is the fact that the system works on a standard PC, capturing the power traces through the recording input of the sound card. Experimental results are presented and confirm that the approach is viable.

Abstract: The present disclosure describes methods, systems, and computer program products for providing remote debugging of a software or cloud application across a wide area network. A method includes transmitting, from a remote communication device to a client or cloud computing device, instructions to adjust a running application to a debugging mode; receiving, at the remote communication device from a server, aggregated thread data in a data packet by using a second debugging data protocol different from the Java Debug Wire Protocol; receiving a debugging command and applying the debugging command to the application running in the debugging mode.

Abstract: Debugging mobile phone applications is hard, as current debugging techniques either require multiple computing devices or do not support graphical debugging. To address this problem we present GROPG, the first graphical on-phone debugger. We implement GROPG for Android and perform a preliminary evaluation on third-party applications. Our experiments suggest that GROPG can lower the overall debugging time of a comparable text-based on-phone debugger by up to 2/3.

Abstract: In various embodiments, a data integration system is disclosed which enables users to debug distributed data integration scenarios which are platform and technology independent. A debugger client can connect to a plurality of local and/or remote hosts executing portions of a distributed data integration scenario. The debugger client can additionally enable line-by-line debugging of the portions of the distributed data integration scenario using a plurality of language-specific interfaces. The language-specific interfaces can further enable the user to dynamically update and debug changes to the code during debugging, reducing the time and resources required by multiple recompilations of the code.

Abstract: Systems and methods for debugging domain specific languages are provided. In accordance with an embodiment, one such system can comprise a web which includes a virtual machine, a debug execution machine, and a domain specific language (DSL)-specific tool interface. The web server is configured to compile DSL code received from a developer computer. During compilation the DSL code is instrumented to include debugging information received from the developer computer. The web server is also configured to execute, by the virtual machine, the instrumented code. During execution the instrumented code communicates with the debug execution machine such that a state of the debug execution machine mirrors a state of the virtual machine.

Abstract: A system and method for a common unified debug architecture for integrated circuits and System on Chips (SoCs) are provided. A system consistent with the present disclosure may comprise of an integrated circuit or SoC which includes a display port, plurality of logic blocks, and debug logic. The debug logic may receive debug data from one or more of the plurality of logic blocks in response to the integrated circuit or SoC operating in a debug mode. In addition, control logic coupled to the debug logic. The control logic provides display data to the display port in response to the integrated circuit operating in an operational mode. The control logic further directs high-speed debug data to the display port in response to the integrated circuit or SoC operating in the debug mode. The high-speed debug data is to be based on the debug data.

Abstract: Methods, apparatuses, and computer program product for distributed debugging of an application in a distributed computing environment are provided. Embodiments include a first debug module on a first host receiving a set breakpoint message from a management debug module of a management system. In response to receiving the set breakpoint message, the first debug module sets a breakpoint for executing a first service on the first host, for the application. Upon hitting the breakpoint while executing the first service for the application, the first debug module sends a breakpoint condition of the first service to the management debug module. In response to receiving the breakpoint condition, the management debug module sends to a second debug module of a second host, an instruction to pause execution of the second service of the second host.

Abstract: Methods and apparatus are provided that facilitate debugging operations for components in dynamic power domains. In an embodiment, an integrated circuit includes hardware sectors associated with observability circuits served by a debug data bus of a debug circuit. A controlled sector residing in a dynamically-controlled power domain may be turned off while the power domain of another sector remains on. To continue to have debug observability all the way through and after these power events, a debug data register is configured to provide data, such as configuration and/or programming data, to the observability circuit of the controlled sector via the debug data bus. A shadow register is configured to capture the data provided to the controlled sector's observability circuit. The shadow register data is used upon restoring power to the controlled sector to restore the controlled sector's observability circuit to a state when the controlled sector was previously powered on.

Abstract: A method provides a debug service in a network environment. One or more processors initiate a debug service as a remote shared service in the network environment. The debug service receives a call from a deployed workload process within a virtual machine in the network environment, and gathers required information for a debug session of the workload process, where the required information includes source code used by the workload process. One or more processors attach the debug service to the workload process to carry out the debug session, such that the debug service working with a debug agent at the workload process attaches to and debugs a virtual environment that obscures the virtual machine.

Abstract: Detecting the effects of transient faults is a key point in many safety-critical applications. This paper explores the possibility of using for this purpose the debug interface existing today in several processors/controllers on the market. In this way one can achieve a good detection capability with respect to control flow errors with very small latency, while the cost for adopting the proposed technique is rather limited and does not involve any change either in the processor hardware or in the application software. The method works even if the processor uses caches. Experimental results are reported, showing both the advantages and the costs of the method.

Abstract: There present invention relates to a multi-core System On Chip (SoC) having a debugging function. The multi-core SoC having a debugging function includes one or more processors each configured to include an On Core Debug (OCD); a bus matrix configured to connect buses between the one or more processors and one or more peripheral devices; and a debug interface configured to include Processor Debug Interfaces (PDIs) for communicating with the respective OCDs and a Bus Debug Interface (BDI) for communicating with the bus matrix. In accordance with the present invention, the function of a multi-core SoC which has become complicated as compared with the existing singe core SoC may be efficiently verified.

Abstract: A debug control system and method thereof which includes a debug device and a wireless communication module. The debug device is configured to communicate electrical data with a target device via a first signal transmission interface. The wireless communication module is configured to communicate electrical data with the debug device via a second communication interface, and is configured to communicate electrical data with a host device. Electrical data exchanged between the debug control system and the target device is configured to debug or update firmware residing on the target device.

Abstract: Side-Channel Analysis plays an important role in cryptology, as it represents an important class of attacks against cryptographic implementations, especially in the context of embedded systems such as hand-held mobile devices, smart cards, RFID tags, etc. These types of attacks bypass any intrinsic mathematical security of the cryptographic algorithm or protocol by exploiting observable side-effects of the execution of the cryptographic operation that may exhibit some relationship with the internal (secret) parameters in the device. Two of the main types of side-channel attacks are timing attacks or timing analysis, where the relationship between the execution time and secret parameters is exploited; and power analysis, which exploits the relationship between power consumption and the operations being executed by a processor as well as the data that these operations work with. For power analysis, two main types have been proposed: simple power analysis (SPA) which relies on direct observation on a single measurement, and differential power analysis (DPA), which uses multiple measurements combined with statistical processing to extract information from the small variations in power consumption correlated to the data. In this thesis, we propose several countermeasures to these types of attacks, with the main themes being timing analysis and SPA. In addition to these themes, one of our contributions expands upon the ideas behind SPA to present a constructive use of these techniques in the context of embedded systems debugging. In our first contribution, we present a countermeasure against timing attacks where an optimized form of idle-wait is proposed with the goal of making the observable decryption time constant for most operations while maintaining the overhead to a minimum. We show that not only we reduce the overhead in terms of execution speed, but also the computational cost of the countermeasure, which represents a considerable advantage in the context of devices relying on battery power, where reduced computations translates into lower power consumption and thus increased battery life. This is indeed one of the important themes for all of the contributions related to countermeasures to side-channel attacks. Our second and third contributions focus on power analysis; specifically, SPA. We address the issue of straightforward implementations of binary exponentiation algorithms (or scalar multiplication, in the context of elliptic curve cryptography) making a cryptographic system vulnerable to SPA. Solutions previously proposed introduce a considerable performance penalty. We propose a new method, namely Square-and-BufferedMultiplications (SABM), that implements an SPA-resistant binary exponentiation exhibiting optimal execution time at the cost of a small amount of storage — O( √ ` ), where ` is the bit length of the exponent. The technique is optimal in the sense that it adds SPA-resistance to an underlying binary exponentiation algorithm while introducing zero computational overhead.

Abstract: The unique promise of embedded systems in FPGAs is that designers can develop and modify their own peripheral hardware with a high degree of flexibility. However, the task of verifying the hardware commonly involves writing software to interact with it. This software itself is prone to design errors. To debug a system with two untested interacting components, it is preferable if their interaction can be precisely traced. We are presenting SimXMD (Simulation-based eXperimental Microprocessor Debugger), a tool that allows developers to debug microcontroller code and custom hardware simultaneously. The concept of debugging hardware and software together is not a new one. However, we take two established tools already used by the respective developers and connect them in a transparent way. SimXMD connects a GNU debugger (GDB) instance to a full-system simulation of an embedded FPGA system in ModelSim. This enables free-roaming investigation of hardware-software interactions inside the system, including reverting back to an earlier moment in simulation time. Software can be debugged in the same way that it would be commonly done with a real implementation on an FPGA board.

Abstract: An apparatus includes a first circuit portion, a second circuit portion, and a control circuit. The first circuit portion may include a first debug circuit. Access to the first debug circuit may be controlled by a first control signal. The second circuit portion may include a second debug circuit. Access to the second debug circuit may be controlled by a second control signal. The second circuit portion is generally controlled according to a secure firmware image. The control circuit may be configured to selectively disable access to the first debug circuit and access to the second debug circuit by generating the first and second control signals. When access to the second debug circuit is disabled, access to the second debug circuit can only be re-enabled by overwriting at least a portion of the secure firmware image.

Abstract: Supporting the online debugging is one of the design goals of SoC. Usually the function unit and the debugging structure are tightly coupled, thus it is hard to reuse the debug structure in other systems. This paper presents an on-chip debug method for SoC bus architecture. The system reuses On Chip Bus(OCB) as the transmission path for debugging data and debugs the units in system in form of bus access through debug interface. To implement debugging of embedded processor, Debug Support Unit and Debug Handle Unit is designed. The method fits for mainstream SoCs. It includes various debug functions and few limitations of debug interface, which is also very efficient. SoC of AMBA architecture with debug architecture of this kind has been implemented, and the debug function has been verified. The experiment indicates that the design satisfies the demand of SoC debugging.

Abstract: Techniques and mechanisms allow a device such as a programmable logic device (PLD) to support real-time debugging of a system. The PLD may be configured to include a debug design without disturbing the configuration of a base logic design in the PLD.

Abstract: The challenges in silicon testing and debug of complex integrated circuits are well understood. Where these circuits include multiple processor cores there is also a dramatic increase in the complexity of verifying and debugging the associated software; with much of this complexity being because of the inherent lack of visibility over internal signals which integration brings. The trend to-date has been to rely upon silicon test interfaces to provide access to internal signals required for software verification and debug. However, it is questionable whether this is sufficient for real-time systems or future designs with increasing processor cores. This study examines the on-chip technology supporting software verification and debug in current designs and proposes enhancements in this area. As much of this technology is primarily intended for silicon test it is lacking in terms of I/O bandwidth, which is a significant limitation for software verification and debug. The authors propose their alternative approach of using an on-chip coprocessor and debug circuitry to address this principal limitation; and describe an embedded application where this approach was successfully applied to monitor timing requirements and detect failures. The authors also outline how this approach could be applied as an architectural solution for formal runtime verification.

Abstract: Debugging parallel and concurrent applications is well-recognized as a time-consuming task, which often requires a significant part of the application development process. In the context of embedded systems, Multi-Processor-System-on-Chip(MPSoC) architectures feature numerous multicore processors which may be coupled with heterogeneous processors like Digital Signal Processors (DSPs) and/or application-specific accelerators. In this situation, it is important that developers are provided with high-level programming environments able to efficiently exploit these architectures, as well as suitable debugging tools. Dataflow programming models were explicitly designed to program parallel architectures and they have the ability to abstract away heterogeneous computing complexity. In addition, the stream-processing aspect of multimedia algorithms naturally exhibits data-dependency graphs, which simplifies application design and implementation. In this paper, we propose a new approach for interactive debugging of dataflow applications. Going beyond the long-established ability of interactive debuggers to support sequential programming languages, we describe the functionalities they should be able to provide to debug embedded and parallel dataflow applications. Then we demonstrate our solution to this problem with a proof-of-concept debugger targeting the dataflow framework used on an industrial MPSoC platform. We also explain the development challenges we faced during the implementation of this GDB-based debugger and illustrate its efficiency through a case study of a video decoder debugging session.

Abstract: An integrated circuit with a high-speed debug access port includes interface circuitry and a dedicated debug port in the interface circuitry. The interface circuitry includes a function circuit block that is used to receive a data packet from external circuitry coupled to the integrated circuit. The dedicated debug port is coupled to the function circuit block and is used to transmit the received data packet to debug circuitry on the integrated circuit. The interface circuitry may include a peripheral component interconnect express (PCIe) interface circuit.

Abstract: To increase program modularity, new languages have been researched in recent years. They allow changing behavior according to various kinds of contexts at the call sites. In our research, we classified them as advanced-dispatching languages. Advanced-dispatching languages are usually implemented as an extension of main-stream languages. After compilation, their programs are transformed to the compiled form of the main-stream language. Due to this compilation mechanism, source-level abstractions cannot be fully restored during debugging. The information loss increases the effort of comprehending advanced-dispatching programs and fixing advanced-dispatching-specific defects. In this thesis, we performed four works to improve the comprehensibility of debugging advanced-dispatching programs on three debugging techniques --- interactive debugging, trace-based debugging, and slicing. Interactive debugging is the most common debugging technique. We proposed eleven atomic advanced-dispatching-specific debugging tasks based on four aspect-oriented-specific fault models. To support the tasks, we modified an existing compiler to keep aspect-oriented information after the compilation, extended java virtual machine, built a dedicated advanced dispatching debugging model, and implemented graphical user interfaces. In interactive debugging, breakpoints set for solving one problem are logically related. However, existing debuggers do not support to build logic between breakpoints. Therefore, programmers have to manually perform some unnecessarily repeated tasks. We analysed five common debugging scenarios and proposed a breakpoint language that uses pointcuts to select suspension times. Interactive debugging cannot support backward inspection, which is required in tracking from an observed behavior to the defect. Trace-based debugging solves this problem by recording events at runtime and then supporting inspection offline. Existing researches on trace-based debugging for advanced-dispatching languages are limited. We proposed a dedicated trace-based debugger with an user interface that allow programmers to navigate and query the recorded trace. Besides debugging techniques performed on runtime inforamtion, we also looked into slicing, which is a static technique that automatically select relevant program statements. It can complement problems of guessing locations for setting breakpoints in interactive debugging and searching relevant information in trace-based debugging. We developed dependency graphs that are dedicated to aspect-oriented programs, as well as a slicing algorithm that is performed on the developed dependency graphs.

Abstract: A debugging system and method, referred to as a kernel functionality checker, is described for enabling debugging of software written for device-specific APIs (application program interfaces) without requiring support or changes in the software driver or hardware. Specific example embodiments are described for OpenCL, but the disclosed methods may also be used to enable debugging capabilities for other device-specific APIs such as DirectX® and OpenGL®.

Abstract: Embodiments of the present invention provide a debugging method, a chip, a board, and a system and relate to the communications field. Remote debugging can be performed on a board having no main control CPU without affecting hardware distribution and software performance. The method includes: receiving, by an Ethernet port, a data packet and determining a current service type according to a service identifier carried in the data packet; when determining the current service type is a debugging service, writing the data packet into a memory through a bus and sending an interruption notification to a CPU through the bus; reading, by the CPU, the data packet from the memory according to the interruption notification, obtaining a debugging instruction by parsing the data packet, and sending the debugging instruction to an ASIC through a protocol conversion module.

Abstract: An Incremental Trace-Based Debug System for Field-Programmable Gate-Arrays Jared M. Keeley Department of Electrical and Computer Engineering, BYU Master of Science Modern society increasingly relies upon integrated circuits (ICs). It can be very costly if ICs do not function properly, and large portions of designer effort are spent on their verification. The use of field-programmable gate arrays (FPGAs) for verification and debug of ICs is increasing. FPGAs are faster than simulation and cost less than fabricating an ASIC prototype. However, the major challenge of using FPGAs for verification and debug is observability. Designers must use special techniques to observe the values of FPGA’s internal signals. This thesis proposes a new method for increasing the observability of FPGAs and demonstrates its feasibility. The new method incrementally inserts trace buffers controlled by a trigger into already placed-and-routed FPGA designs. Incremental insertion allows several drawbacks of typical trace-based approaches to be avoided such as influencing the placing and routing of the design, large area overheads, and slow turnaround times when changes must be made to the instrumentation. It is shown that it is possible to observe every flip flop in Xilinx Virtex-5 designs using the method, given that enough trace buffer capacity is available. We investigate factors that influence the results of the method. It is shown that making the trace buffers wide may lead to routing failures. Congested areas of the circuit must be avoided when placing the trigger or this may also lead to routing failures. A drawback of the method is that it may increase the minimum period of the design, but we show that pipelining can reduce these effects. The method proves to be a promising way to observe thousands of signals in a design, potentially allowing designers to fully reconstruct the internal values of an FPGA over multiple clock cycles to assist in verification and debug.

Abstract: To improve debugging turnaround time of complex System-on-chip (SoC) designs on FPGA based logic emulation systems, it is important to minimize the iterations through design recompilation or FPGA reconfiguration process for validating repeated debugging changes This paper presents a methodology for modeling debugging changes in terms of standalone assertion statements and evaluating their effect by running emulation without requiring any design modification or recompilation step, during emulation based debug The set of assertions representing debugging changes are transformed into a set of constraints that are directly programmed into the emulator and an associated logic analyzer When emulation is resumed from a bug-free state, these constraints are enforced by automatically forcing necessary signals to desired values, according to the specified assertions Multiple debugging changes can thus be verified before eventually porting the fixes to design RTL followed by recompilation and emulation rerun The proposed methodology also facilitates block based SoC development, by allowing a designer to enforce the correct functional behavior of some other block whose output affects the behavior of the block he is working on Application of the proposed debugging system to debugging of real industry standard designs has been seen to reduce debugging turn-around time significantly

Abstract: The share of silicon debug in the overall microprocessor chips development cycle is rapidly expanding due to the ever growing design complexity and the limited efficiency of pre-silicon validation methods. Massive application of short random test programs on the prototype microprocessor chips is one of the most effective parts of silicon debug. However, a major bottleneck and source of "noise" in this phase is that large numbers of random test programs fail due to the same or similar design bugs. This redundant behavior adds long delays in the debug flow since each failing random program must be separately examined, although it does not usually bring new debug information. The development of effective techniques that detect dominant modes of failure among random programs and triage them into common categories eliminate redundant debug sessions and significantly boost silicon debug.We propose the employment of deconfigurable microprocessor architectures along with self-checking random test programs to reduce the redundant debug sessions and make the triage step of silicon debug more efficient. Several hardware components of high performance microprocessor micro-architectures can be deconfigured while keeping the functional completeness of the design. This is the property we exploit in our silicon debug methodology for the triaging of random test programs. We support our methodology by a hardware mechanism dedicated to silicon debug that groups the failing test programs into categories depending on the microprocessor hardware components that need to be deconfigured for a random test program to be correctly executed. Identical deconfiguration sequences for multiple test programs indicate the existence of redundancy among them and group them together. This grouping significantly reduces the number of failing tests that must be debugged afterwards. Detailed evaluation of the method on an x86 microprocessor demonstrates its efficiency in reducing the debug sessions and thus in accelerating silicon debug.

Abstract: PURPOSE: A vehicle ECU debugging system and a method thereof are provided to accurately analyze software in detail by preventing the reset of an ECU even though the software of the ECU is debugged based on JTAG(Joint Test Action Group)/BDM(Background Debug Mode) protocols. CONSTITUTION: Debuggers(60,70) debug software of an ECU installed in a vehicle. A first converting module(40) is connected with the ECU and converts a first protocol used for communication with the ECU and a second protocol used for a vehicle network. A second converting module(50) is installed in the outside of the vehicle to be connected with the vehicle network, performs communication with the first converting module based on the second protocol, communicates with the debuggers based on the first protocol, and mutually converts the first and the second protocols. [Reference numerals] (40) First converting module; (50) Second converting module; (60) MCU debugger; (70) DSP debugger