Abstract: Debug of at-speed failures using functional tests is a key challenge as part of frequency pushes during post-silicon debug to improve performance of high performance designs, especially microprocessors. In this paper, we present a technique to automate the debug of speed path failures using failing functional tests by extracting information from design-for-debug features and then algorithmically isolating the internal speed-paths that could be the source of the failures. Results from application of the technique during silicon debug on the Intel ® Core ™ i7 quad-core processor is presented.

Abstract: Problems in a new System on Chip (SOC) consisting of hardware and embedded software often only show up when a silicon prototype of the chip is placed in its intended target environment and the application is executed. Traditionally, the debugging of embedded systems is difficult and time consuming because of the intrinsic lack of internal system observability and controlability in the target environment. Design for Debug (DfD) is the act of adding debug support to the design of a chip, in the realization that not every SOC is correct first time. DfD provides debug engineers with increased observability and controlability of the internal operation of an embedded system. In this paper, we present a monitoring infrastructure for multi-processor SOCs with a Network on Chip (NOC), and explain its application to performance analysis and debug. We describe how our monitors aid in the performance analysis and debug of the interactions of the embedded processors. We present a generic template for bus and router monitors, and show how they are instantiated at design time in our NOC design flow. We conclude this paper with details of their hardware cost.

Abstract: A large part of a modern SOC's debug complexity resides in the interaction between the main system components. Transaction-level debug moves the abstraction level of the debug process up from the bit and cycle level to the transactions between IP blocks. In this paper we raise the debug abstraction level further, by utilising structural and temporal abstraction techniques, combined with debug data interpretation and logical communication views. The combination of these techniques and views allow us, among others, to single-step and observe the operation of the network on a per-connection basis. As an example, we show how these higher-level abstractions have been implemented in the debug environment for the AEthereal NOC architecture and present a generic debug API, which can be used to visualise an SOC's state at the logical communication level.

Abstract: A semiconductor chip may be operable to block the debug interfaces when the semiconductor chip boots up from the boot read-only memory (ROM). The semiconductor chip may be operable to authenticate a debug certificate received by the semiconductor chip and enable one or more debug interfaces in the semiconductor chip based on the information resulting from the authentication of the debug certificate. The debug certificate may be in a form of a cryptographic public key certificate. A unique device ID which may be generated at boot and stored in the memory may be used by the semiconductor chip to authenticate the debug certificate. The device ID may be generated using the cryptographic public key that is stored in the one-time programmable (OTP) memory in the semiconductor chip and a cryptographic hash algorithm.

Abstract: While the complexity of System-on-a-Chip (SoC) design keeps growing rapidly today the need for an efficient approach to catch design errors at silicon stage has become an urgent issue. In this paper we present a platform for silicon debugging that makes use of an existing test architecture and thus can provide many powerful debug features while requiring very low extra overhead. It supports multi-core debugging for general purpose cores in an SOC chip with the capabilities of on-line tracing, hardware breakpoint insertion and cycle-based stepping. An automatic design tool is also developed to cooperate with the debug platform. Together users can easily control debug operations and examine trace results to efficiently identify the root cause of failures in the silicon.

Abstract: Cross platform debugging can make the software debugging and hardware platform developing work simultaneity in embedded system development, which accelerates the development lifecycle dramatically. Reverse execution can run program backward to historic points, may provide programmers with a useful approach of fast locating the cause of the program failure. In this paper, we propose a reversible debugging framework for cross debugging and implement a prototype reversible debugger called Reversible Debugger for Cross Platform (RDXP) on X86/Linux platform based on PORD. The evaluation shows that RDXP provides an efficient and portable software debugging environment with reasonable speed and memory consumption.

Abstract: Transactional Memory (TM) has received a lot of attention as a programming API for concurrent programs on emerging multicore architectures. If the transactional programming model is to realize its promise of simplifying the problem of writing correct and scalable concurrent programs, debuggers will have to change. In this paper, we introduce tm db, an open-source library to provide debuggers with a general debugging support for transactional programs. The library helps debuggers provide programmers with generic transactional debugging features, independent of the particular TM’s runtime internals. In addition, it provides TM designers with a well defined interface for transactional debugging support. We discuss the basic debugging features we believe are essential to debug transactional programs, how they are provided by the library, and how they integrate into a general debugging infrastructure.

Abstract: Provided is a web-based software debugging apparatus and method for remote debugging The web-based software debugging apparatus may include: a web interface to provide a web browser that enables a user to make a request for a debugging service for software performed in a remote target system, and to verify a debugging result of the software; a debugger client to receive the debugging service request for the software via the web interface, and to provide the debugging result to the web interface; and a debugger server to receive the debugging service request from the debugger client, and to transmit the debugging result to the debugger client after debugging the software through a connection to the target system according to the debugging service request

Abstract: A data processing system having debug message generation uses processor circuitry to perform a plurality of processor operations. Global control circuitry is coupled to the processor circuitry. Debug circuitry is coupled to the global control circuitry for generating debug messages corresponding to predetermined processor operations. Message generation logic provides debug messages which selectively include a timestamp field providing information as to when a debug message is generated. Debug control circuitry is coupled to the global control circuitry and the message generation logic and has a timestamp control register. For each of a plurality of debug message types, the timestamp control register selectively enables or disables appending a timestamp to the debug message for that type of debug message. Enable logic is coupled to the timestamp control register for enabling or disabling the timestamp control register based on detecting a selected event in the data processing system.

Abstract: A computer-implemented method, system, and computer program product for a web-based integrated test and debugging system is provided. The method includes configuring a proxy widget on a server to communicate with a debug widget on a browser, and configuring the proxy widget to communicate with an integrated development environment (IDE) external to the server. The method also includes running a process on the server associated with one or more process-control widgets on the browser. The method further includes polling the IDE via the proxy widget to access a debug and test infrastructure of the IDE for debug data associated with the process, and relaying the debug data associated with the process from the proxy widget to the debug widget to provide web-based integration of testing and debugging on the browser while the process is running on the server.

Abstract: Traditional debug facilities are limited in providing debugging requirements for multicore parallel programming. Synchronization problems or bugs due to race conditions are particularly difficult to detect with software debugging tools. This work presents a fast and feasible hardware-assistant solution for many-core non-intrusive debugging. The key idea is to keep tracks of data accesses of shared memory areas and their lock synchronization activities by proposed data structures in proposed debugging IP (dIP). A page-based shared variable cache is provided to keep shared variables as long as possible, and an inexpensive pluggable off-chip RAM can eliminate the false-positive rate efficiently. To decrease the debugging traffic block, this work provides a thread library to specify shared memory/lock events and transmit those events to the dIP by a small proper hardware co-processor (eXtend dIP) of each core. Our experimental result shows the debugging traffic block (worse-case) by increasing cores, and adding tolerance buffers in XdIP can efficiently ease off. Moreover, the real workloads (SPLASH-2, MPEG-4, and H.264) are executed by the dIP non-instructive race-detection with only 4.7%~12.2% slow down in average. Finally, the hardware cost of dIP is also low when the growing of many-core.

Abstract: A distributed debug system including processing elements connected to perform a plurality of processing functions on a received data unit, a debug trap unit, a debug trace dump logic unit, and a debug initiator unit is provided. At least two of the processing elements include a debug trap unit that has a first debug enable input and output, and a first debug thread. The first debug thread holds at least a first debug trap circuit having a match signal output connected to the first debug enable output. The first debug trap circuit filters a part of the data unit, compares a filtering result with a debug value, and provides a match signal to the match signal output. The debug trace dump logic unit dumps debug trace data to a buffer associated with the data unit on reception of a match event. The debug initiator unit includes a debug initiator output connected to the first debug enable input of the debug trap unit of one processing element, and a debug initiator input connected to the first debug enable output of the debug trap unit of another processing element.

Abstract: IEEE Std 1149.1-2001 Standard Test Access Port and Boundary-Scan Architecture (JTAG) is widely used as a debug interface, providing a path for a debugger to access debug components in complex systems-on-chip (SoCs). By its very nature JTAG accommodates systems containing multiple devices. However, JTAG was primarily intended as a component and board test interface, and is not ideally suited as a debug interface. Its shortcomings have led the industry to search for an alternative. As a result, JTAG interfaces have started to be displaced by dedicated debug interfaces. This paper examines some of these alternatives, and concludes that a dedicated serial wire debug interface can be delivered with lower pin-count and higher performance, whilst maintaining support for multi-device systems and interoperability with test.

Abstract: As the complexity of System-on-a-Chip (SOC) design keeps growing rapidly, efficient and economic testing and debugging for complex circuits at silicon stage has become extremely important. In this paper we present a unified platform that facilitates efficient on-chip testing and silicon debugging in a PC-based environment. Test techniques including scan and BIST, and debug functions including online tracing, hardware breakpoint insertion and cycle-based single-stepping, are supported in this platform. An automatic design tool is also developed to simplify the generation and application of the platform. With this platform users can easily carry out structural testing with the scan or BIST test mode, functional verification with the on-line tracing mode, and fault diagnosis with the single-step mode.

Abstract: Relative Debugging allows a user to compare the internal state of two programs as they run, making it possible to test whether two programs perform the same function given the same input. When implemented with a command line user interface, a relative debugger looks like traditional debugging tools with the addition of commands that describe which structures should be equivalent in the two programs. In this paper, we discuss relative debugging within an integrated development environment, and show that there are significant advantages over a command line form. We describe a pluggable, modular, architecture that works with a variety of different products, including Microsoft's Visual Studio, SUN's NetBeans, and IBM's Eclipse. Copyright © 2009 John Wiley & Sons, Ltd.

Abstract: Designing System-on-a-Chip (SoC) using system-level languages is becoming a standard in industry. However, the non-deterministic semantics of such parallel languages could yield failures that are hard to debug. In this paper, we present a new approach that supports automatic debugging of SoC designs written in SystemC using a method that isolates failure-inducing process schedules.

Abstract: The fine-grained parallelism inherent in FPGAs has encouraged their use in packet processing systems. Debugging and performance evaluation of such complex designs can be significantly improved through debug information that provides a system-level perspective and hides the complexity of signal-level debugging. In this paper we present a debugging system that permits transaction-based communication-centric monitoring of packet processing systems. We demonstrate, using two different examples, how this system can improve the debugging information and abstract lower level detail. Furthermore, we demonstrate that transaction monitoring systems require fewer resources than conventional RTL debugging systems and can provide a system-level perspective not permitted by traditional tools.

Abstract: Standard debuggers are limited in the amount of analysis that they perform in order to assist with debugging. This paper presents UDB, a source-level debugger for the Unicon programming language with a novel architecture and capabilities. UDB combines classical debugging techniques such as those found in GDB with a growing set of automatic debugging extensions. UDB tests the hypotheses that a debugger built on top of a high-level framework enables better debugging capabilities as well as easier and more efficient extension than ordinary debuggers.

Abstract: With the development of integrated circuit technology, it is more difficult to test and debug. Usually, design for testability (DFT) and debugging structure are made separately in VLSI, which need a great deal of additional hardware resource. This paper introduces a testing structure designed in microprocessor based on JTAG, which is based on scan-set technology, combined with the boundary scan and internal scan technology. This testing structure integrates with DFT and debugging logic, which avoids many scan chains hardware expenses and reduces the cost of design and verification. This structure can supply high fault coverage near 100%, and debugging ability through JTAG port, which only increases the difficulty of the circuit logic design and is applicable to all general-purpose microprocessor chips.

Abstract: Any application software will inevitably contain bugs during the development cycle. In order to correct these software flaws, developers need access to powerful debugging tools that allow them to be more efficient as well as be able to dig into the detailed operation of their application. Therefore, the debugger is a comparatively important tool in software development, particularly in the embedded software development. The paper analyses and studies the embedded debugging technique of stub mode. It adopts the remote serial communication protocol of GNU GDB, and takes over all exception handlers by software to implement debugging and tracking of object program. It realizes to read and to write memory units and registers, to set breakpoint, single step and to continue running. Stub mode is applied to RTEMS embedded real-time operating system and application program for debugging based on ARM.

Abstract: Debugging of multi-agent systems (MAS) is hard due to their distributed, concurrent, adaptive, highly interactive, flexible, mobile and heterogeneous nature.We identify three dimensions (activities, scale, and coupling) that span the area of debugging and derive general requirements for a debugging toolset in the multi-agent context. An implementation of a toolset w.r.t. the requirements given for the MAS reference architecture Mulan is presented. This toolset comprises general low level debugging possibilities that are included in the virtual machine (execution engine Renew), specialized Mulan-dependent debugging facilities that enable debugging on higher (agent concepts and independent debugging aspects that rely on publicly available information - i.e. message logs - together with advanced techniques, such as visualization and mining.

Abstract: The Idaho Debugging Extension Architecture (IDEA) enables dynamic analysis agents, such as automatic debugging and visualization agents, to be loaded on the fly in a source-level debugger. IDEA is an event-driven debugging architecture that provides a simple interface to load API-compliant external dynamic analysis agents during a debugging session. Multiple standalone agents can be loaded and managed under the control of the source-level debugger. Successful agents can be migrated into the source code of the debugger core as permanent features with higher performance.

Abstract: The present invention provides a web-based software debugging apparatus for remote debugging and a method thereof. The web-based software debugging apparatus comprises: a web interface for providing a web browser with which the user is able to demand a debugging service for software performed in a remote target system and to confirm the debugging result of the software; a debugger client which receives the demand for the debugging service for the software through the web interface, and provides the debugging result of the software to the web interface; and a debugger server which receives the demand for the debugging service from the debugger client, and transmits the debugging result to the debugger client after debugging the software through the connection with the target system according to the demand for the debugging service.

Abstract: The solution to debug a problem in a deeply embedded system is to integrate the debug and communication module inside the chip. In this paper, we propose an on-chip in-circuit emulation (ICE) architecture for debugging an asynchronous Java accelerator core which can be integrated with any existing processor and operating system. The operation of this ICE module and the debug strategy of the Java accelerator are specifically designed for asynchronous implementation. They not only facilitate the system development but also provide a manufacture test method for asynchronous chips. KeywordsAsychronous; Java accelerator; In-circuit Emulation; On-chip

Abstract: This article describes a comprehensive approach for silicon debug of a server chipset that includes a high-performance, third-generation chip-multithreaded (CMT) Sparc microprocessor. Efficiently debugging the chipset required a combination of debug features in silicon and system platforms, firmware support for debug, test generation tools, and debug data interpretation tools. Several useful lessons were learned in the process.

Abstract: A verification platform for SoC debug system based on SystemVerilog direct programming interface (DPI) is presented and implemented. The platform integrates software debugger GDB and the verification Testbench for target device to debug the debug system of ARM7 SoC when the design is in RTL-level phase. With the platform,the problems or errors in debug system can be found and located before FPGA prototype verifiction. The efficiency of debug system verification can be improved by using the platform.